公开(公告)号：US10515900B2

公开(公告)日：2019-12-24

申请号：US16222047

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L23/495 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.

公开(公告)号：US20190252339A1

公开(公告)日：2019-08-15

申请号：US16396782

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ai-Tee Ang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/1191 ,  H01L2224/18 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/95001

Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.

公开(公告)号：US10283377B1

公开(公告)日：2019-05-07

申请号：US15832742

申请日：2017-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Yao-Tong Lai

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes at least one die, a plurality of conductive structures, an encapsulant, an enhancement layer, and a redistribution structure. The die has an active surface and includes a plurality of conductive posts on the active surface. The conductive structures surround the die. The encapsulant partially encapsulates the die. The enhancement layer is over the encapsulant. A top surface of the enhancement layer is substantially coplanar with top surfaces of the conductive posts and the conductive structures. A material of the enhancement layer is different from a material of the encapsulant. A roughness of an interface between the encapsulant and the enhancement layer is larger than a roughness of the top surface of the enhancement layer. The redistribution structure is over the enhancement layer and is electrically connected to the conductive structures and the die.

公开(公告)号：US10276537B2

公开(公告)日：2019-04-30

申请号：US15715132

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ai-Tee Ang ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Ching-Yao Lin

IPC: H01L27/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/00

Abstract: An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively leveled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are leveled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is leveled with the active surfaces. The second surface of the encapsulant is leveled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant.

公开(公告)号：US09960246B2

公开(公告)日：2018-05-01

申请号：US15369460

申请日：2016-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Lian ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Chih-Wei Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/517 ,  H01L21/28158 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.

公开(公告)号：US09515158B1

公开(公告)日：2016-12-06

申请号：US14918054

申请日：2015-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Lian ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Chih-Wei Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/517 ,  H01L21/28158 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. In addition, the insertion layer is made of M1Ox, and M1 is a metal, O is oxygen, and x is a value greater than 4.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括衬底，在衬底上形成的界面层，以及形成在界面层上的插入层。 半导体结构还包括形成在插入层上的栅极电介质层和形成在栅极介电层上的栅极结构。 此外，插入层由M1Ox制成，M1为金属，O为氧，x为大于4的值。

公开(公告)号：US12288729B2

公开(公告)日：2025-04-29

申请号：US18435362

申请日：2024-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20240386744A1

公开(公告)日：2024-11-21

申请号：US18789792

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chih-Hua Chen ,  Yu-Jen Cheng ,  Chih-Wei Lin ,  Yu-Feng Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: G06V40/13 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

公开(公告)号：US12033965B2

公开(公告)日：2024-07-09

申请号：US18312325

申请日：2023-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Yi-Ming Dai

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L24/03 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/3171 ,  H01L23/5226 ,  H01L24/08

Abstract: A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.

公开(公告)号：US12009345B2

公开(公告)日：2024-06-11

申请号：US18149509

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.