公开(公告)号：US20200373219A1

公开(公告)日：2020-11-26

申请号：US16993285

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

公开(公告)号：US10811384B2

公开(公告)日：2020-10-20

申请号：US16713009

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/538 ,  H01L23/29

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

公开(公告)号：US20200303364A1

公开(公告)日：2020-09-24

申请号：US16898409

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/34 ,  H01L21/56

Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

公开(公告)号：US20200243497A1

公开(公告)日：2020-07-30

申请号：US16260115

申请日：2019-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Ming-Hsien Tsai

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L23/36

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

公开(公告)号：US10672681B2

公开(公告)日：2020-06-02

申请号：US15965989

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chang Lin ,  Hsin-Yu Pan ,  Lipu Kris Chuang ,  Ming-Chang Lu

IPC: H01L23/373 ,  H01L25/10 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first sub-package and a second sub-package. The first sub-package includes a first die, a graphite oxide layer on the first die and an encapsulant encapsulating the first die and the graphite oxide layer. The second sub-package is stacked on and electrically connected to the first sub-package, and includes a second die. The graphite oxide layer is disposed between the first die and the second die.

公开(公告)号：US20190333836A1

公开(公告)日：2019-10-31

申请号：US15965989

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chang Lin ,  Hsin-Yu Pan ,  Lipu Kris Chuang ,  Ming-Chang Lu

IPC: H01L23/373 ,  H01L25/10 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first sub-package and a second sub-package. The first sub-package includes a first die, a graphite oxide layer on the first die and an encapsulant encapsulating the first die and the graphite oxide layer. The second sub-package is stacked on and electrically connected to the first sub-package, and includes a second die. The graphite oxide layer is disposed between the first die and the second die.

公开(公告)号：US20250022825A1

公开(公告)日：2025-01-16

申请号：US18510523

申请日：2023-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin ,  Hsin-Yu Pan

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/58

Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.

公开(公告)号：US20240404991A1

公开(公告)日：2024-12-05

申请号：US18328430

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Min-Chien Hsiao ,  Kuo-Chiang Ting ,  Yen-Ming Chen ,  Ashish Kumar Sahoo ,  Chen-Sheng Lin ,  Hsin-Yu Pan

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Embodiments include methods of forming three-dimensional packages and the packages resulting therefrom. The packages may utilize a bridge die to electrically connect one die to another die and at least one additional die adjacent to the bridge die. The height-to-width ratio of the gap between the bridge die and the at least one additional die is controlled by thinning the bridge die to be thinner than the at least one additional die. The packages may utilize landing structures to adjoin a dielectric material of an attached die to a metallic landing structure of a base die.

公开(公告)号：US20240274483A1

公开(公告)日：2024-08-15

申请号：US18630049

申请日：2024-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Teng-Yuan Lo ,  Lipu Kris Chuang ,  Hsin-Yu Pan

IPC: H01L23/24 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/24 ,  H01L21/4846 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/81815 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

公开(公告)号：US20240234340A1

公开(公告)日：2024-07-11

申请号：US18151545

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Yuan Sheng Chiu ,  Hong-Yu Guo ,  Hsin-Yu Pan ,  Tsung-Shu Lin

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08147 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2924/0544 ,  H01L2924/05494

Abstract: An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.