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    Passivation scheme design for wafer singulation
    32.
    发明授权
    Passivation scheme design for wafer singulation 有权

    公开(公告)号：US12249580B2

    公开(公告)日：2025-03-11

    申请号：US18358530

    申请日：2023-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Ming-Fa Chen

    IPC: H01L23/00 ,  H01L21/74 ,  H01L21/78 ,  H01L23/31 ,  H01L23/525 ,  H01L23/544 ,  H01L23/58

    Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.

    STRUCTURE AND METHOD FOR FORMING INTEGRATED HIGH DENSITY MIM CAPACITOR
    38.
    发明申请
    STRUCTURE AND METHOD FOR FORMING INTEGRATED HIGH DENSITY MIM CAPACITOR 有权

    公开(公告)号：US20210391413A1

    公开(公告)日：2021-12-16

    申请号：US16901912

    申请日：2020-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

    IPC: H01L49/02 ,  H01L21/768 ,  H01G4/30 ,  H01L23/522

    Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

    Packaging scheme involving metal-insulator-metal capacitor
    39.
    发明授权
    Packaging scheme involving metal-insulator-metal capacitor 有权

    公开(公告)号：US11133304B2

    公开(公告)日：2021-09-28

    申请号：US16697797

    申请日：2019-11-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsiang-Ku Shen ,  Ying-Ju Chen ,  Hsien-Wei Chen

    IPC: H01L23/64 ,  H01L27/06 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L49/02 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/768

    Abstract: A device includes a first die and a second die. The first die includes: a first substrate that contains first electrical circuitry, a first interconnection structure disposed over the first substrate, a first dielectric layer disposed over the first interconnection structure, and a plurality of first bonding pads disposed over the first dielectric layer. The second die includes: a second substrate that contains second electrical circuitry, a second interconnection structure disposed over the second substrate, a second dielectric layer disposed over the second interconnection structure, and a plurality of second bonding pads disposed over the second dielectric layer. The first bonding pads of the first die are bonded to the second bonding pads of the second die. At least one of the first die or the second die includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes more than two metal layers that are stacked over one another.

    Redistribution layer structures for integrated circuit package
    40.
    发明授权
    Redistribution layer structures for integrated circuit package 有权

    公开(公告)号：US11056433B2

    公开(公告)日：2021-07-06

    申请号：US16883210

    申请日：2020-05-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chen-Hua Yu

    IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

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