公开(公告)号：US11746003B2

公开(公告)日：2023-09-05

申请号：US17711067

申请日：2022-04-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Chaung-Lin Lai ,  Shu-Ming Chang

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B7/0074 ,  B81C1/00301 ,  B81B2207/07

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US11705368B2

公开(公告)日：2023-07-18

申请号：US17373773

申请日：2021-07-13

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L21/76894 ,  H01L21/02013 ,  H01L24/94

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US10833118B2

公开(公告)日：2020-11-10

申请号：US15001065

申请日：2016-01-19

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L27/146

Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

公开(公告)号：US10109663B2

公开(公告)日：2018-10-23

申请号：US15258594

申请日：2016-09-07

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Tsang-Yu Liu ,  Yi-Ming Chang ,  Hsin Kuan

IPC: H01L27/146

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

公开(公告)号：US10049252B2

公开(公告)日：2018-08-14

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Hsing-Lung Shen

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498 ,  G06F3/041

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

公开(公告)号：US09997473B2

公开(公告)日：2018-06-12

申请号：US15409289

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/52 ,  H01L21/54 ,  H01L23/18 ,  H01L23/055 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

公开(公告)号：US09685354B2

公开(公告)日：2017-06-20

申请号：US14676478

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC: B26D1/09 ,  H01L21/67 ,  H01L21/683 ,  B26D7/18

CPC classification number: H01L21/67092 ,  B26D1/095 ,  B26D7/1863 ,  H01L21/6838 ,  Y10T83/0267 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/364

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body. The cap layer is pressed against by the bottom surface of the suction pad and sucked by the suction pad of the vacuum nozzle head after the vacuum pump begins to vacuum the air within the hollow vacuum pipe and the through hole. Then, the first cutter cuts into the interface between the substrate and the cap layer, and the cap lay is separated from the substrate by the suction force of the vacuum nozzle head and the lift force generated by the upward movement of the vacuum nozzle head.

公开(公告)号：US09653422B2

公开(公告)日：2017-05-16

申请号：US14673657

申请日：2015-03-30

Applicant: XINTEC INC.

Inventor： Chia-Lun Shen ,  Yi-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/306 ,  H01L21/48

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L21/48 ,  H01L21/78 ,  H01L24/05 ,  H01L24/09 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

公开(公告)号：US09640488B2

公开(公告)日：2017-05-02

申请号：US15008202

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Yi-Min Lin ,  Yi-Ming Chang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L29/06 ,  H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

公开(公告)号：US09601460B2

公开(公告)日：2017-03-21

申请号：US14618413

申请日：2015-02-10

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Shu-Ming Chang ,  Tzu-Wen Tseng

IPC: H01L23/06 ,  H01L23/00 ,  H01L23/31 ,  H01L29/06 ,  H01L23/525

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.