公开(公告)号：US20070086166A1

公开(公告)日：2007-04-19

申请号：US11580869

申请日：2006-10-16

申请人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

发明人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC分类号： H05K7/20

CPC分类号： H01L21/6835 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599

摘要： In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.

摘要翻译： 在半导体模块的制造方法中，在支撑基板上形成金属层。 然后，在金属层上形成第一导电柱和第一绝缘层。 第一绝缘层围绕第一导电柱的侧面。 然后，在第一导电柱上形成第二导电柱。 第二导电柱电连接到第一导电柱。 然后，形成第二绝缘层以覆盖第二导电柱。 第二绝缘层由粘合树脂制成。 最后，通过第二绝缘层将半导体器件粘附到第二导电柱，同时第一半导体器件和第一绝缘层之间的间隙被第二绝缘层密封。

公开(公告)号：US20070080449A1

公开(公告)日：2007-04-12

申请号：US11541536

申请日：2006-10-03

申请人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

发明人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC分类号： H01L23/48

CPC分类号： H01L23/49866 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/09 ,  H05K3/205 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0315 ,  H05K2203/1173

摘要： An interconnect substrate 10 includes an insulating resin layer 12 (base material), an interconnect 14 and an electrode pad 16. On the insulating resin layer 12, the interconnect 14 and the electrode pad 16 are provided. The interconnect 14 and the electrode pad are integrally formed. A first metal material, exposed in the surface S1 of the electrode pad 16 opposite to the insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material, exposed in the surface S2 of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.

摘要翻译： 互连基板10包括绝缘树脂层12（基材），互连14和电极焊盘16。 在绝缘树脂层12上设置有互连件14和电极垫16。 互连14和电极焊盘是一体形成的。 暴露在电极焊盘16的与绝缘树脂层12相反并构成电极焊盘16的表面S1中的第一金属材料在表面S 2中暴露于具有比第二金属材料形成氧化物的更高的自由能 与绝缘树脂层12相对并构成互连件14。

公开(公告)号：US20070026662A1

公开(公告)日：2007-02-01

申请号：US11491180

申请日：2006-07-24

申请人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

IPC分类号： H01L21/4763

CPC分类号： H05K3/423 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/113 ,  H05K1/114 ,  H05K3/025 ,  H05K3/064 ,  H05K2203/016 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

摘要翻译： 根据本发明的实施例的制造方法包括在支撑衬底70上形成种子金属层20a，在种子金属层20b上形成包括互连18的互连层10，在形成后去除支撑衬底70 互连层10，并且图案化种子金属层20a，从而在去除支撑衬底之后形成互连20。

公开(公告)号：US20060226556A1

公开(公告)日：2006-10-12

申请号：US11393686

申请日：2006-03-31

申请人： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

发明人： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83051 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H05K3/4644 ,  H05K3/4676 ,  H05K3/4688 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/0401

摘要： The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20 is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip 30. An end face of the via plug 44 on the side of the interconnect layer 10 is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls 60. The thermal decomposition temperature of the insulating resin 14 constituting the interconnect layer 10 is higher than that of the insulating resin 24 constituting the interconnect layer 20.

摘要翻译： 半导体器件1包括互连层10,20，IC芯片30，经由插头42,44，密封树脂50和焊球60。 互连层10包括通孔塞42。 通孔插头42在互连层20一侧的端面的面积比相对端面即IC芯片30一侧的端面小。 通孔插头44在互连层10一侧的端面的面积小于相对端面，即焊球60一侧的端面。 构成互连层10的绝缘树脂14的热分解温度高于构成互连层20的绝缘树脂24的热分解温度。

公开(公告)号：US08456020B2

公开(公告)日：2013-06-04

申请号：US12906377

申请日：2010-10-18

申请人： Yoichiro Kurita ,  Masaya Kawano

发明人： Yoichiro Kurita ,  Masaya Kawano

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/60 ,  H01L24/24 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.

摘要翻译： 半导体封装具有：第一芯片; 和第二芯片。 第一芯片具有：形成在第一芯片的主表面上的绝缘树脂层; 在所述绝缘树脂层的区域中形成为贯通所述绝缘树脂层并电连接到所述第二芯片的凸点状的第一内部电极组， 用于与外部设备电连接的外部电极组; 和与外部电极组电连接的静电放电保护元件组。 第一内部电极组不与静电放电保护元件组电连接。

公开(公告)号：US08058165B2

公开(公告)日：2011-11-15

申请号：US12853660

申请日：2010-08-10

申请人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H05K3/423 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/113 ,  H05K1/114 ,  H05K3/025 ,  H05K3/064 ,  H05K2203/016 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

摘要翻译： 根据本发明的实施例的制造方法包括在支撑衬底70上形成种子金属层20a，在种子金属层20a上形成包括互连18的互连层10，在形成互连之后移除支撑衬底70 层10，并且图案化种子金属层20a，从而在移除支撑衬底之后形成互连20。

公开(公告)号：US08030201B2

公开(公告)日：2011-10-04

申请号：US12635160

申请日：2009-12-10

申请人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H01L21/44

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

摘要翻译： 第一电子电路部件和第二电子电路部件分别经由第一焊料和第二焊料电连接到导电部件。 导电构件形成在树脂膜中。 导电构件被构造成包含第二扩散阻挡金属膜。 第二扩散阻挡金属膜防止第二焊料的扩散。 在导电构件和第一焊料之间设置有第一扩散阻挡金属膜。 第一扩散阻挡金属膜防止第一焊料的扩散。 在树脂膜的第一表面和导电部件上形成粘接金属膜，以与树脂膜和导电部件接触。 粘合金属膜比第一焊料和第一扩散阻挡金属膜中的任一种具有比树脂膜更强的粘附性。

公开(公告)号：US07800233B2

公开(公告)日：2010-09-21

申请号：US11491180

申请日：2006-07-24

申请人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/423 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/113 ,  H05K1/114 ,  H05K3/025 ,  H05K3/064 ,  H05K2203/016 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

摘要翻译： 根据本发明的实施例的制造方法包括在支撑衬底70上形成种子金属层20a，在种子金属层20a上形成包括互连18的互连层10，在形成互连之后移除支撑衬底70 层10，并且图案化种子金属层20a，从而在去除支撑衬底之后形成互连20。

公开(公告)号：US07598590B2

公开(公告)日：2009-10-06

申请号：US11143672

申请日：2005-06-03

申请人： Masaya Kawano ,  Tsutomu Tashiro ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Tsutomu Tashiro ,  Yoichiro Kurita

IPC分类号： H01L29/66

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L23/564 ,  H01L2224/32145

摘要： The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed on the insulating layer 14 with the layered structure. The semiconductor substrate 10 has a circuit forming region A1 provided in the silicon layer 16. An insulating region 18 is provided on the semiconductor substrate 10. The insulating region 18 is provided so as to surround the entire side face of the circuit forming region A1.

摘要翻译： 半导体芯片1具有半导体基板10.在本实施方式中，作为SOI基板的半导体基板10由支撑基板12，形成在支撑基板12上的层叠结构的绝缘层14构成， 以及形成在具有层状结构的绝缘层14上的硅层16。 半导体衬底10具有设置在硅层16中的电路形成区域A.绝缘区域18设置在半导体衬底10上。绝缘区域18设置成围绕电路形成区域A1的整个侧面。

公开(公告)号：US20080203565A1

公开(公告)日：2008-08-28

申请号：US12114238

申请日：2008-05-02

申请人： Yoichiro KURITA ,  Masaya Kawano ,  Koji Soejima

发明人： Yoichiro KURITA ,  Masaya Kawano ,  Koji Soejima

IPC分类号： H01L23/498

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83051 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H05K3/4644 ,  H05K3/4676 ,  H05K3/4688 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/0401

摘要： The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20 is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip 30. An end face of the via plug 44 on the side of the interconnect layer 10 is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls 60. The thermal decomposition temperature of the insulating resin 14 constituting the interconnect layer 10 is higher than that of the insulating resin 24 constituting the interconnect layer 20.

摘要翻译： 半导体器件1包括互连层10,20，IC芯片30，经由插头42,44，密封树脂50和焊球60。 互连层10包括通孔塞42。 通孔插头42在互连层20一侧的端面的面积比相对端面即IC芯片30一侧的端面小。 通孔插头44在互连层10一侧的端面的面积小于相对端面，即焊球60一侧的端面。 构成互连层10的绝缘树脂14的热分解温度高于构成互连层20的绝缘树脂24的热分解温度。