Abstract:
Structures and related processes for effectively regulating power among slave chips in a 3D memory multichip package that employs TSVs for interlevel chip connections. Individual voltage regulators are employed on one or more of the slave chips for accurate level control of internal voltages, for example, word line driver voltage (VPP), back bias voltage (VBB), data line voltage (VDL), and bit line pre-charge voltage/cell plate voltage (VBLP/VPL). Employing regulators on one or more of the slave chips not only allows for precise regulation of power levels during typical memory stack operation, but also provides tolerance in small variations in power levels caused, for example, by manufacturing process variations. Moreover, less chip real estate is used as compared to techniques that provide complete power generators on each chip of a multichip stack.
Abstract:
A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.
Abstract:
A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command.
Abstract:
A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.
Abstract:
Disclosed is a semiconductor device that comprises a plurality of through-silicon vias (TSVs), a signal line and a selective connector for causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, based on a control signal.
Abstract:
Management of congestion level, in a computer-related context, is disclosed. Also disclosed is a system generating a plurality of computer network-related tables during system operation. A number of the tables are each separately indexed by a different index. The system includes at least one tangible computer-readable medium adapted to store, at each indexed location, a swap count providing an indication of the congestion level of the indexed location. The system also includes insert logic stored as instructions on the at least one medium for execution. When executed, the insert logic is operable to: i) insert, when a predetermined condition has been satisfied, a new entry by overwriting the current entry stored in the indexed location having the lowest swap count; and ii) update the swap counts in each of the indexed locations in a manner that maintains the total swap count at least substantially constant over time.
Abstract:
Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
Abstract:
A method and apparatus for starting an internal combustion engine is disclosed. A motor is mechanically coupled to the engine, the engine having at least one moveable element mounted in a chamber, the moveable element being operable to cause a changing compression condition within the chamber and being mechanically coupled to a shaft for generating mechanical power. The method involves causing the motor to supply a positioning torque to the engine to move the at least one moveable element into a starting position. The method also involves causing the motor to supply a starting torque to the engine when the at least one moveable element is in the starting position to cause the moveable element to accelerate from the starting position under low compression conditions to generate sufficient momentum to overcome a peak compression condition in the chamber, thereby reducing the starting torque required to start the engine.
Abstract:
A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
Abstract:
A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.