Voltage regulation for 3D packages and method of manufacturing same
    31.
    发明授权
    Voltage regulation for 3D packages and method of manufacturing same 有权
    3D封装的电压调节及其制造方法

    公开(公告)号:US08913443B2

    公开(公告)日:2014-12-16

    申请号:US13236381

    申请日:2011-09-19

    Inventor: Hong Boem Pyeon

    Abstract: Structures and related processes for effectively regulating power among slave chips in a 3D memory multichip package that employs TSVs for interlevel chip connections. Individual voltage regulators are employed on one or more of the slave chips for accurate level control of internal voltages, for example, word line driver voltage (VPP), back bias voltage (VBB), data line voltage (VDL), and bit line pre-charge voltage/cell plate voltage (VBLP/VPL). Employing regulators on one or more of the slave chips not only allows for precise regulation of power levels during typical memory stack operation, but also provides tolerance in small variations in power levels caused, for example, by manufacturing process variations. Moreover, less chip real estate is used as compared to techniques that provide complete power generators on each chip of a multichip stack.

    Abstract translation: 用于在采用TSV进行层间芯片连接的3D存储器多芯片封装中有效调节从芯片之间的功率的结构和相关过程。 单个电压调节器用于一个或多个从芯片,用于内部电压的精确电平控制,例如字线驱动器电压(VPP),反偏压(VBB),数据线电压(VDL)和位线预 充电电压/电池板电压(VBLP / VPL)。 在一个或多个从属芯片上采用稳压器不仅允许在典型的存储器堆栈操作期间对功率电平进行精确的调节,而且还提供例如由制造工艺变化引起的功率电平的小变化中的容限。 此外,与在多芯片堆叠的每个芯片上提供完整功率发生器的技术相比,使用更少的芯片空间。

    System including a plurality of encapsulated semiconductor chips
    32.
    发明授权
    System including a plurality of encapsulated semiconductor chips 有权
    系统包括多个封装的半导体芯片

    公开(公告)号:US08908378B2

    公开(公告)日:2014-12-09

    申请号:US13917728

    申请日:2013-06-14

    Inventor: Jin-Ki Kim

    Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

    Abstract translation: 公开了一种固态驱动器。 固态驱动器包括具有相对的第一和第二表面的电路板。 多个半导体芯片附接到固态驱动器的电路板的第一表面,并且固态驱动器的多个半导体芯片包括至少基本上封装在树脂中的至少一个存储器芯片。 还公开了一种在线存储器模块型形状电路板。 在线存储器模块型外形电路板具有相对的第一和第二表面。 多个半导体芯片附接到直列式存储模块型形状电路板的第一表面,并且这些半导体芯片包括至少基本上封装在树脂中的至少一个存储芯片。

    Simultaneous read and write data transfer
    33.
    发明授权
    Simultaneous read and write data transfer 有权
    同时读写数据传输

    公开(公告)号:US08898415B2

    公开(公告)日:2014-11-25

    申请号:US13962062

    申请日:2013-08-08

    CPC classification number: G06F3/0659 G06F3/061 G06F3/0688 G06F13/4243

    Abstract: A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command.

    Abstract translation: 用于布置存储器件的控制器可以发出写入命令而不等待先前发出的读取命令的接收。 寻址的存储器件可以根据读取命令将数据读出到数据总线上,同时根据读取命令之后接收的写入命令写入数据。

    Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit
    34.
    再颁专利
    Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit 有权
    具有占空比校正电路的延迟锁定环和延迟锁定环的占空比校正电路

    公开(公告)号:USRE45247E1

    公开(公告)日:2014-11-18

    申请号:US13405703

    申请日:2012-02-27

    Applicant: Chan-kyung Kim

    Inventor: Chan-kyung Kim

    CPC classification number: H03L7/0812 H03K5/133 H03K5/1565

    Abstract: A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

    Abstract translation: 包括占空比校正电路的占空比校正电路和延迟锁定环(DLL)能够控制其工作,以正确地分析当在DLL中产生占空比误差时产生占空比误差的原因 。 占空比校正电路选择性地输出到用于在切换控制信号的控制下控制与外部时钟信号同步的内部时钟信号的占空比的DLL核心占空比偏移信息。 DLL根据占空比偏移信息校正参考时钟信号的占空比,从而输出占空比为50%的参考时钟信号。

    Congestion management in a network
    36.
    发明授权
    Congestion management in a network 有权
    网络中的拥塞管理

    公开(公告)号:US08855121B2

    公开(公告)日:2014-10-07

    申请号:US13795070

    申请日:2013-03-12

    Inventor: David Brown

    Abstract: Management of congestion level, in a computer-related context, is disclosed. Also disclosed is a system generating a plurality of computer network-related tables during system operation. A number of the tables are each separately indexed by a different index. The system includes at least one tangible computer-readable medium adapted to store, at each indexed location, a swap count providing an indication of the congestion level of the indexed location. The system also includes insert logic stored as instructions on the at least one medium for execution. When executed, the insert logic is operable to: i) insert, when a predetermined condition has been satisfied, a new entry by overwriting the current entry stored in the indexed location having the lowest swap count; and ii) update the swap counts in each of the indexed locations in a manner that maintains the total swap count at least substantially constant over time.

    Abstract translation: 在计算机相关的背景下披露拥塞程度的管理。 还公开了在系统操作期间生成多个计算机网络相关表的系统。 多个表分别由不同的索引分别索引。 该系统包括至少一个有形的计算机可读介质,其适于在每个索引的位置处存储提供索引位置的拥塞级别的指示的交换计数。 该系统还包括存储为用于执行的至少一个介质上的指令的插入逻辑。 当执行时,插入逻辑可操作为:i)当已经满足预定条件时,通过重写存储在具有最低交换次数的索引位置中的当前条目来插入新条目; 以及ii)以保持总交换计数至少基本上恒定的方式来更新每个索引位置中的交换计数。

    Dual function compatible non-volatile memory device
    39.
    发明授权
    Dual function compatible non-volatile memory device 有权
    双功能兼容的非易失性存储设备

    公开(公告)号:US08837237B2

    公开(公告)日:2014-09-16

    申请号:US14026359

    申请日:2013-09-13

    Inventor: Jin-Ki Kim

    CPC classification number: G11C16/06 G11C5/14 G11C5/143 G11C7/20 G11C16/20

    Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

    Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器,异步和同步命令解码器,开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式,并提供适当的开关选择信号。 开关网络响应于开关选择信号,通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号,并提供公共控制逻辑与启动相应操作的必要信号。

    Semiconductor memory device suitable for interconnection in a ring topology
    40.
    发明授权
    Semiconductor memory device suitable for interconnection in a ring topology 有权
    适用于环形拓扑互连的半导体存储器件

    公开(公告)号:US08825939B2

    公开(公告)日:2014-09-02

    申请号:US12141384

    申请日:2008-06-18

    CPC classification number: G11C16/10 G06F13/4239 G11C7/10 G11C7/1003

    Abstract: A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device.

    Abstract translation: 一种半导体存储器件,包括:存储器; 用于接收命令锁存使能信号,地址锁存使能信号,信息信号和指示存储器件是否被控制器选择的选择信号的多个输入; 多个输出,用于向下一个装置释放一组输出信号; 控制电路; 和旁路电路。 当选择信号指示由控制器选择的存储器件时,控制电路被配置为基于命令锁存使能信号和地址锁存使能信号来解释信息信号。 当选择信号指示存储器件未被控制器选择时,旁路电路被配置为将命令锁存使能信号,地址锁存使能信号和信息信号传送到存储器件的输出。

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