公开(公告)号：US5880993A

公开(公告)日：1999-03-09

申请号：US941882

申请日：1997-09-30

Applicant: Alan Kramer ,  Roberto Canegallo ,  Mauro Chinosi ,  Giovanni Gozzini ,  Pier Luigi Rolandi ,  Marco Sabatini

Inventor： Alan Kramer ,  Roberto Canegallo ,  Mauro Chinosi ,  Giovanni Gozzini ,  Pier Luigi Rolandi ,  Marco Sabatini

IPC: G01R31/28 ,  G11C11/56 ,  G11C16/02 ,  G11C16/34 ,  G11C29/12 ,  G11C29/50 ,  G11C16/06

CPC classification number: G11C16/3486 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3481 ,  G11C27/005 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: To check the programming of a nonvolatile memory cell storing an actual threshold value, the drain terminal of the cell is biased at a constant voltage; the gate terminal is biased at a check voltage; the cell is supplied with a predetermined current to determine a gate-source voltage drop related to the actual threshold value; and the voltage at the source terminal is supplied to an input of an operational amplifier. In an open-loop configuration, the desired threshold value of the set predetermined current is supplied as the check voltage; the amplifier compares the source voltage with the ground; and switching of the amplifier indicates the desired threshold value has been reached. In a closed-loop configuration, the output of the operational amplifier is connected directly to the gate terminal of the cell, and supplies the desired threshold value directly.

Abstract translation: 为了检查存储实际阈值的非易失性存储单元的编程，单元的漏极端子被偏置为恒定电压; 栅极端子被偏置在检查电压; 向单元提供预定电流以确定与实际阈值相关的栅极 - 源极电压降; 并且源极端子处的电压被提供给运算放大器的输入端。 在开环配置中，将所设定的预定电流的期望阈值作为检查电压被提供; 放大器将源电压与地相比较; 并且放大器的切换指示已经达到期望的阈值。 在闭环配置中，运算放大器的输出直接连接到单元的栅极端，并直接提供所需的阈值。

公开(公告)号：US5874852A

公开(公告)日：1999-02-23

申请号：US706068

申请日：1996-08-30

Applicant: Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

Inventor： Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

IPC: G05F3/26 ,  H03F3/345 ,  H03F3/343

CPC classification number: H03F3/345 ,  G05F3/267

Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg by an impedance matching circuit configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

Abstract translation: 具有可控频率响应的电流发生器电路具有由MOS晶体管形成的至少一个电流镜，其通过保持在恒定电压的端子供电，具有输入支路，参考电流（I1）由第一电流发生器 G1），并且具有用于在镜的输出端（OUT）上产生与参考电流（I1）成比例的镜像电流（Iout）的输出支路。 输入支路至少包括二极管连接的第一晶体管（M1），并且具有通过阻抗匹配电路耦合到包括在输出支路中的第二晶体管（M2）的对应端子（Ga2）的控制端子（Ga1） 被配置为在两个端子（Ga1和Ga2）处保持相同的电压值。 阻抗匹配电路具有可调节的输出阻抗，具体值低于没有该电路的值。 它用于调节第二晶体管（M2）的控制节点（Ga2）上的阻抗。 本发明同样适用于N沟道和P沟道MOS晶体管。 有利地，参考电流可以通过作为输出信号的函数的外部信号来改变，以提供反馈调节特征。

公开(公告)号：US5864562A

公开(公告)日：1999-01-26

申请号：US869859

申请日：1997-06-05

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G11C29/80 ,  G11C29/808

Abstract: In a memory device equipped with a redundancy circuit comprising at least one redundancy memory register storing a defective address of a defective memory element and an identifying code suitable for identifying a portion of a matrix of memory elements wherein the defective memory element is located, a circuit for transferring redundancy data of a redundancy circuit inside the memory device is provided. The circuit comprises a shared bus of signal lines provided in the memory device to interconnect a plurality of circuit blocks of the memory device and for transferring signals between the circuit blocks. The shared bus can be selectively to the various circuit blocks, and a bus assignment circuit associated to the redundancy circuit is provided for assigning, during a prescribed time interval of a read cycle of the memory device, the shared bus to the redundancy circuit whereby in the prescribed time interval the identifying code stored in the redundancy memory register can be transferred onto the shared bus.

Abstract translation: 在配备有冗余电路的存储器件中，该冗余电路包括存储有缺陷存储元件的缺陷地址的至少一个冗余存储器寄存器和适合于识别缺陷存储器元件所在的存储元件矩阵的一部分的识别码， 用于传送存储装置内的冗余电路的冗余数据。 电路包括设置在存储器件中的信号线的共享总线，用于互连存储器件的多个电路块并用于在电路块之间传送信号。 共享总线可以选择性地连接到各种电路块，并且提供与冗余电路相关联的总线分配电路，用于在存储器件的读取周期的规定时间间隔内将共享总线分配给冗余电路，由此在 存储在冗余存储器寄存器中的识别码的规定时间间隔可以被传送到共享总线上。

公开(公告)号：US5864258A

公开(公告)日：1999-01-26

申请号：US846873

申请日：1997-05-01

Applicant: Paolo Cusinato ,  Melchiorre Bruccoleri

Inventor： Paolo Cusinato ,  Melchiorre Bruccoleri

IPC: H03K3/013 ,  H03K3/03 ,  H03L7/099 ,  H03L7/183 ,  H03B5/04 ,  H03K3/354

CPC classification number: H03K3/013 ,  H03K3/0315 ,  H03L7/0995 ,  H03L7/183

Abstract: A voltage-controlled oscillator, with high noise rejection of the supply voltage, includes a plurality of delay cells in an odd number N.gtoreq.3, which are connected to form a first ring oscillator and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR. The VCO comprises at least one second ring oscillator formed by a plurality of delay cells in an odd number M.gtoreq.3, at least one of which is also a delay cell of the first oscillator and at least two of which do not belong to the first oscillator. At least one of these two cells is powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.

Abstract translation: 具有电源电压的高噪声抑制的压控振荡器包括奇数N 3 / = 3中的多个延迟单元，其连接形成第一环形振荡器，并由电源电压Vcc 和可变调节电压VR。 VCO包括由奇数M> / = 3中的多个延迟单元形成的至少一个第二环形振荡器，其中至少一个延迟单元也是第一振荡器的延迟单元，并且其中至少两个不属于 第一个振荡器。 这两个电池中的至少一个由恒定电压（Vcc）供电，使得两个振荡器以相同的频率工作，并且两个振荡器之间的相互作用引入了具有有效效果的高频负反馈 降低电源电压Vcc的噪声。

公开(公告)号：US5862226A

公开(公告)日：1999-01-19

申请号：US798618

申请日：1997-02-11

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: H04H20/72 ,  H04H40/27 ,  H04L27/26 ,  H04H5/00

CPC classification number: H04H40/27 ,  H04L27/2647 ,  H04H20/72 ,  H04H2201/20

Abstract: The broadcast mode of the different ones set by the international standards for digital audio broadcasting (DAB) according to a coded orthogonal frequency division multiplexing scheme (COEFDM) may be automatically detected in a receiver through a detection routine. Many of the calculation modules required by the automatic mode detection system of the invention are already present in a receiver and can be exploited for performing the digital signal processing that leads to an automatic recognition of the broadcast mode of the station on which the receiver is tuned.

Abstract translation: 可以通过检测程序在接收机中自动检测根据编码正交频分复用方案（COEFDM）的数字音频广播（DAB）国际标准设定的不同播送模式。 本发明的自动模式检测系统所需的许多计算模块已经存在于接收机中，并且可以用于执行数字信号处理，这导致对其上调谐接收机的站的广播模式的自动识别 。

公开(公告)号：US5851855A

公开(公告)日：1998-12-22

申请号：US795697

申请日：1997-02-04

Applicant: Giuseppe Ferla ,  Ferruccio Frisina

Inventor： Giuseppe Ferla ,  Ferruccio Frisina

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L49/00

CPC classification number: H01L24/06 ,  H01L23/4824 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41741 ,  H01L29/7802 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107

Abstract: A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates are connected, through a respective bonding wire, to a respective pin of the package.

Abstract translation: 一种用于制造MOS技术功率器件芯片和封装组件的工艺，所述MOS技术功率器件芯片包括其中集成有多个基本功能单元的半导体材料层，每个基本功能单元贡献相当于总电流的分数 并且包括形成在所述半导体层中的第一导电类型的第一掺杂区域和形成在所述第一掺杂区域内的第二导电类型的第二掺杂区域; 所述包装件包括用于外部电气和机械连接的多个销; 多个基本功能部件由多个基本功能单元组成，每个子多个元件的所有基本功能单元的第二掺杂区域与与第二掺杂的金属板电绝缘的相同金属板接触 其他子复数的所有基本功能单元的区域; 每个金属板通过相应的接合线连接到封装的相应引脚。

公开(公告)号：US5825250A

公开(公告)日：1998-10-20

申请号：US757384

申请日：1996-11-27

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

IPC: H03F1/08 ,  H03F1/14

CPC classification number: H03F1/086

Abstract: An integrated operational amplifier with adjustable frequency compensation having a transconductance input stage and an amplifier output stage connected serially together between an input terminal and an output terminal of the operational amplifier. For the purpose of frequency compensation, moreover, a compensation block is connected across the input and the output of the output stage. The compensation block uses a plurality of charge storage elements connected in parallel together and in series with switch block which selects a sub-plurality of said charge storage elements in response to an external signal of the amplifier. The compensation block thereby provides an overall effective capacitance for frequency compensation.

Abstract translation: 具有可变频率补偿的集成运算放大器，具有串联连接在运算放大器的输入端和输出端之间的跨导输入级和放大器输出级。 此外，为了频率补偿的目的，在输出级的输入端和输出端之间连接补偿块。 补偿块使用并联连接并与开关块串联的多个电荷存储元件，该开关块响应于放大器的外部信号选择子多个所述电荷存储元件。 因此，补偿块为频率补偿提供总体有效电容。

公开(公告)号：US5825138A

公开(公告)日：1998-10-20

申请号：US721437

申请日：1996-09-27

Applicant: Claudio Diazzi ,  Mario Tarantola ,  Fabrizio Martignoni

Inventor： Claudio Diazzi ,  Mario Tarantola ,  Fabrizio Martignoni

IPC: H05B41/295 ,  G05F1/00

CPC classification number: H05B41/295

Abstract: The need of implementing a second local oscillator in addition to the drive oscillator, for timing the different phases of the starting process of a half-bridge or bridge stage driving an external load, such as a fluorescent lamp, is avoided by employing a timing counter to count the number of oscillations produced by the drive oscillator, and a digital-to-analog converter for controlling the frequency of oscillation of the drive oscillator.

Abstract translation: 除了驱动振荡器之外实现第二本地振荡器的需要，用于定时驱动诸如荧光灯的外部负载的半桥或桥接台的启动过程的不同阶段，通过采用定时计数器 以计数由驱动振荡器产生的振荡的数量，以及用于控制驱动振荡器的振荡频率的数模转换器。

公开(公告)号：US5821781A

公开(公告)日：1998-10-13

申请号：US855020

申请日：1997-05-12

Applicant: Luca Rigazio

Inventor： Luca Rigazio

IPC: H03K3/03 ,  H03K19/00

CPC classification number: H03K3/03

Abstract: Generator of clock pulses having a period selectable between a first period, a second period of greater duration than that of the first period and a third period, with duration imposed by the transitions of a synchronization signal (SYNC) from a first to a second logic level, comprising: a resettable oscillator controlled by a binary selection signal having a first and second logic level, in order to generate periodic pulses having the first or second period depending on the logic level of the said selection signal, the oscillator comprising a pulse extractor triggered by the periodic pulses and by the transitions from first to second logic level of the synchronization signal in order to generate, with each pulse and transition received as input, one of the said periodic clock pulses, acting as reset signal for the oscillator, and a finite state logic machine, having at least two states A, B and inputs for receiving the synchronization signal and the periodic pulses, and generating the selection signal at a first logic level, in state A, and at the second logic level in state B, the machine evolving from state to state as a function of the signals and received as input.

Abstract translation: 具有时钟脉冲发生器，其具有在第一周期，比第一周期和第三周期的持续时间更长的第二周期之间可选择的周期，持续时间由同步信号（SYNC）从第一逻辑到第二逻辑 电平，包括：由具有第一和第二逻辑电平的二进制选择信号控制的可复位振荡器，以便根据所述选择信号的逻辑电平产生具有第一或第二周期的周期脉冲，所述振荡器包括脉冲提取器 由周期性脉冲和由同步信号的第一至第二逻辑电平的转变触发，以便在作为输入接收的每个脉冲和转换中产生充当振荡器的复位信号的所述周期性时钟脉冲之一，以及 有限状态逻辑机器，具有至少两个状态A，B和用于接收同步信号和周期性脉冲的输入，并且产生 选择信号处于第一逻辑电平，处于状态A，而处于状态B的第二逻辑电平时，机器根据信号从状态演变为状态并作为输入接收。

公开(公告)号：US5818257A

公开(公告)日：1998-10-06

申请号：US749971

申请日：1996-11-14

Applicant: Nuccio Villa

Inventor： Nuccio Villa

IPC: H03K3/356 ,  H03K17/10 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/017

CPC classification number: H03K19/018521 ,  H03K17/102 ,  H03K19/00315 ,  H03K3/356113

Abstract: An interface circuit for coupling the output of an integrated circuit designed for a relatively low supply voltage to a circuit designed to operate at a higher supply voltage employs a cascoded architecture and makes use of two purposely derived reference voltages. The circuit comprises a level rising stage, an output buffer stage (off chip driver stage), an overdrive stage for the pull-up device of the output buffer and a drain follower stage, the pull-up element of which is driven by a second output node of the level rising stage and the pull-down element of which is driven by the inverted input data stream.

Abstract translation: 用于将设计用于较低电源电压的集成电路的输出耦合到设计成在较高电源电压下工作的电路的接口电路采用级联架构并利用两个有目的地导出的参考电压。 电路包括电平上升级，输出缓冲级（片外驱动级），用于输出缓冲器的上拉器件的过驱动级和漏极跟随器级，其上拉元件由第二级驱动 输出节点，其下拉元件由反相输入数据流驱动。