公开(公告)号：US10002801B2

公开(公告)日：2018-06-19

申请号：US15597285

申请日：2017-05-17

Applicant: HITACHI, LTD.

Inventor： Misuzu Sagawa ,  Tetsufumi Kawamura

IPC: H01L21/00 ,  B81C1/00 ,  H01L21/66 ,  H01L21/306 ,  H01L21/67 ,  B81C99/00

CPC classification number: H01L22/20 ,  B81C1/00547 ,  B81C99/0025 ,  B81C99/0065 ,  B81C2201/0142 ,  H01L21/30604 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/67259

Abstract: The device manufacturing method includes a length measuring step (S5) of, on the basis of an observation target image of an SEM image taken from a direction having a predetermined angle from a direction perpendicular to a plane of a substrate, measuring the thickness of a target object, or the depth of etching, formed on the substrate. In addition, in the length measuring step, an etching angle made by a cross section of the etching and the direction perpendicular to the plane of the substrate is calculated from processing data of the target object, and the thickness of the target object or the depth of the etching is measured on the basis of the calculated etching angle.

公开(公告)号：US20180005906A1

公开(公告)日：2018-01-04

申请号：US15597285

申请日：2017-05-17

Applicant: HITACHI, LTD.

Inventor： Misuzu SAGAWA ,  Tetsufumi KAWAMURA

IPC: H01L21/66 ,  B81C1/00 ,  H01L21/306 ,  H01L21/67

CPC classification number: H01L22/20 ,  B81C1/00547 ,  B81C99/0025 ,  B81C99/0065 ,  B81C2201/0142 ,  H01L21/30604 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/67259

Abstract: The device manufacturing method includes a length measuring step (S5) of, on the basis of an observation target image of an SEM image taken from a direction having a predetermined angle from a direction perpendicular to a plane of a substrate, measuring the thickness of a target object, or the depth of etching, formed on the substrate. In addition, in the length measuring step, an etching angle made by a cross section of the etching and the direction perpendicular to the plane of the substrate is calculated from processing data of the target object, and the thickness of the target object or the depth of the etching is measured on the basis of the calculated etching angle.

公开(公告)号：US20170256416A1

公开(公告)日：2017-09-07

申请号：US15435838

申请日：2017-02-17

Applicant: Lam Research Corporation

Inventor： Andreas Fischer ,  Thorsten Lill ,  Richard Janek ,  John Boniface

IPC: H01L21/311 ,  C23F1/00 ,  H01J37/32

CPC classification number: H01L21/31122 ,  B81C2201/0135 ,  B81C2201/0142 ,  C23C16/0245 ,  C23F1/00 ,  C23F1/12 ,  C23F4/00 ,  H01J37/32009 ,  H01J37/32082 ,  H01J2237/334 ,  H01L21/30655 ,  H01L21/32136

Abstract: A method for performing atomic layer etching (ALE) on a substrate, including the following method operations: performing a surface modification operation on a surface of the substrate, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer; performing a removal operation on the substrate surface, the removal operation configured to remove the modified layer from the substrate surface, wherein removing the modified layer occurs via a ligand exchange reaction that is configured to volatilize the modified layer; performing, following the removal operation, a plasma treatment on the substrate surface, the plasma treatment configured to remove residues generated by the removal operation from the substrate surface, wherein the residues are volatilized by the plasma treatment; repeating the foregoing operations until a predefined thickness has been etched from the substrate surface.

公开(公告)号：US20170073224A1

公开(公告)日：2017-03-16

申请号：US15312146

申请日：2015-05-05

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Yonggang HU ,  Guoping ZHOU

IPC: B81C1/00

CPC classification number: B81C1/00619 ,  B81C1/00 ,  B81C2201/0133 ,  B81C2201/0142

Abstract: An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is snore precise. and the uniformity and the homogeneity of the formed support beam are better.

Abstract translation: 用于制造传感器的基于MEMS的方法包括以下步骤：在衬底（100）的前表面上形成浅沟道（120）和支撑梁（140）; 在所述衬底（100）的前表面上形成第一外延层（200）以密封所述浅沟道（120）; 在所述第一外延层（200）下方形成悬浮网状结构（160）; 以及在与所述浅通道（120）相对应的所述基板（100）的背表面上的位置处形成深通道（180），使得所述浅通道（120）与所述深通道（180）连通。 在制造基于MEMS的传感器的方法中，当在前表面上形成浅沟道时，形成质量块的支撑梁，因此通道的蚀刻更易于控制，工艺打鼾精确。 形成的支撑梁的均匀性和均匀性更好。

公开(公告)号：US08585916B2

公开(公告)日：2013-11-19

申请号：US12812986

申请日：2009-01-21

Applicant: Thomas D. Perroud ,  Kamlesh D. Patel ,  Robert J. Meagher

Inventor： Thomas D. Perroud ,  Kamlesh D. Patel ,  Robert J. Meagher

IPC: B31D3/00

CPC classification number: G01N33/5005 ,  B01F3/0807 ,  B01F5/0471 ,  B01F13/0059 ,  B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L3/502776 ,  B01L3/502784 ,  B01L2200/0668 ,  B01L2300/0816 ,  B01L2300/0864 ,  B01L2400/0688 ,  B81B2201/058 ,  B81C1/00047 ,  B81C1/00087 ,  B81C1/00119 ,  B81C1/00404 ,  B81C2201/0133 ,  B81C2201/0142 ,  Y10T137/9464 ,  Y10T428/24479

Abstract: Disclosed herein are methods of making micropores of a desired height and/or width between two isotropic wet etched features in a substrate which comprises single-level isotropic wet etching the two features using an etchant and a mask distance that is less than 2× a set etch depth. Also disclosed herein are methods using the micropores and microfluidic devices comprising the micropores.

Abstract translation: 本文公开的方法是在衬底中的两个各向同性湿蚀刻特征之间制造所需高度和/或宽度的微孔的方法，其包括使用蚀刻剂和小于2×一组的掩模距离的单层各向同性湿蚀刻两个特征 蚀刻深度。 本文还公开了使用包括微孔的微孔和微流体装置的方法。

公开(公告)号：US20120074598A1

公开(公告)日：2012-03-29

申请号：US13248087

申请日：2011-09-29

Applicant: Franz-Peter Kalz

Inventor： Franz-Peter Kalz

IPC: H01L23/28 ,  B23K26/00

CPC classification number: B81C1/00801 ,  B23K2103/50 ,  B81C2201/0142 ,  B81C2201/0143

Abstract: In various embodiments, a chip may include a substrate; a coating, the coating covering the substrate at least partially and the coating being designed for being stripped at least partially by means of laser ablation; wherein between the substrate and the coating, a laser detector layer is arranged at least partially, the laser detector layer being designed for generating a detector signal for ending the laser ablation.

Abstract translation: 在各种实施例中，芯片可以包括衬底; 涂层，所述涂层至少部分地覆盖所述基底，并且所述涂层被设计为至少部分地通过激光烧蚀剥离; 其中在所述基底和所述涂层之间，至少部分地布置有激光检测器层，所述激光检测器层被设计为产生用于结束所述激光烧蚀的检测器信号。

公开(公告)号：US07900350B2

公开(公告)日：2011-03-08

申请号：US11373521

申请日：2006-03-10

Applicant: Taku Masai ,  Koji Sano

Inventor： Taku Masai ,  Koji Sano

IPC: H05K3/02

CPC classification number: H05K7/06 ,  B81B2207/097 ,  B81C1/00301 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0142 ,  B81C2203/0109 ,  B81C2203/036 ,  H01L2924/16235 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49156

Abstract: A circuit element comprises a wiring board; the wiring board comprises a substrate and a wiring formed on the substrate, and a lid joined on the substrate containing a part of the wiring with a binder and making a sealed space above the substrate, wherein if a spot of the wiring joined with the lid by a binder is a spot of junction, a flank of both flanks of the wiring comprise bends in the spot of junction.

Abstract translation: 电路元件包括布线板; 布线板包括基板和形成在基板上的布线，以及盖子，其接合在基板上，该基板包含布线的一部分，并具有粘合剂并且在基板上方形成密封空间，其中如果布线与盖子接合的点 通过粘合剂是接合点，布线两侧的侧面包括在接合部位的弯曲部。

公开(公告)号：US20090218312A1

公开(公告)日：2009-09-03

申请号：US12467942

申请日：2009-05-18

Applicant: Philip D. Floyd ,  William J. Cummings

Inventor： Philip D. Floyd ,  William J. Cummings

IPC: B44C1/22

CPC classification number: H01L21/3065 ,  B81B2201/047 ,  B81C1/00531 ,  B81C2201/0142 ,  B81C2201/056 ,  G02B26/001 ,  H01L21/32135 ,  H01L21/67069

Abstract: Provided herein is an apparatus and a method useful for manufacturing MEMS devices. An aspect of the disclosed apparatus provides a substrate comprising an etchable material exposed to a solid-state etchant, wherein the substrate and the solid-state etchant are disposed in an etching chamber. In some embodiments, the solid state etchant is moved into close proximity to the substrate. In other embodiments, a configurable partition is between the substrate and the solid-state etchant is opened. The solid-state etchant forms a gas-phase etchant suitable for etching the etchable material. In some preferred embodiments, the solid-state etchant is solid xenon difluoride. The apparatus and method are advantageously used in performing a release etch in the fabrication of optical modulators.

Abstract translation: 本文提供了一种用于制造MEMS装置的装置和方法。 所公开的装置的一个方面提供了一种包括暴露于固态蚀刻剂的可蚀刻材料的衬底，其中衬底和固态蚀刻剂设置在蚀刻室中。 在一些实施例中，固态蚀刻剂移动到靠近基板的位置。 在其它实施例中，可配置的分隔件在基板之间并且打开固态蚀刻剂。 固态蚀刻剂形成适于蚀刻可蚀刻材料的气相蚀刻剂。 在一些优选的实施方案中，固态蚀刻剂是固体氙二氟化物。 该装置和方法有利地用于在光学调制器的制造中执行释放蚀刻。

公开(公告)号：US07435355B2

公开(公告)日：2008-10-14

申请号：US11242866

申请日：2005-10-05

Applicant: Wei-Chin Lin ,  Hui-Ling Chang ,  Ching-Hsiang Tsai ,  Chao-Chiun Liang ,  Gen-Wen Hsieh ,  Yuh-Wen Lee

Inventor： Wei-Chin Lin ,  Hui-Ling Chang ,  Ching-Hsiang Tsai ,  Chao-Chiun Liang ,  Gen-Wen Hsieh ,  Yuh-Wen Lee

IPC: B44C1/22 ,  H01L21/302

CPC classification number: H01L21/02052 ,  B81B2201/12 ,  B81C1/00626 ,  B81C2201/0142 ,  G01Q60/38

Abstract: A liquid-based gravity-driven etching-stop technique for controlling structure dimension is provided, where opposite etching trenches in cooperation with an etching-stop solution are used for controlling the dimension of a microstructure on the wafer level. In an embodiment, opposite trenches surrounding the microstructure are respectively etched on sides of the wafer, and the trench depth on the side of the wafer, on which the microstructure is, is equal to the design dimension of the microstructure. Contrarily, it is unnecessary to define the trench depth on the back-side of the chip. In the final step of the fabrication process, when the device is etched, such that the trenches on the sides communicate with each other to separate the microstructure from the whole wafer automatically and thereby shift from the etchant into the etching-stop solution to stop etching.

Abstract translation: 提供了一种用于控制结构尺寸的液体重力驱动蚀刻停止技术，其中与蚀刻停止溶液配合的相反蚀刻沟槽用于控制晶片级上的微结构的尺寸。 在一个实施例中，围绕微结构的相对的沟槽分别蚀刻在晶片的侧面上，并且在其上的晶片侧面上的沟槽深度等于微结构的设计尺寸。 相反，不需要在芯片的背面限定沟槽深度。 在制造过程的最后步骤中，当器件被蚀刻时，使得侧面上的沟槽彼此连通以自动地将微结构与全部晶片分离，从而从蚀刻剂移动到蚀刻停止溶液中以停止蚀刻 。

公开(公告)号：US07303934B2

公开(公告)日：2007-12-04

申请号：US10531934

申请日：2003-10-17

Applicant: Jozef Thomas Martinus Van Beek ,  Margot Van Grootel

Inventor： Jozef Thomas Martinus Van Beek ,  Margot Van Grootel

IPC: H01L21/00

CPC classification number: B81C1/00595 ,  B81B2203/0323 ,  B81C2201/0142

Abstract: The invention relates to a method of manufacturing a micro-electromechanical device (10), in which are consecutively deposited on a substrate (1) a first electroconductive layer (2) in which an electrode (2A) is formed, a first electroinsulating layer (3) of a first material, a second electroinsulating layer (4) of a second material different from the first material, and a second electroconductive layer (5) in which a second electrode (5A) lying opposite the first electrode is formed which together with the first electrode (2A) and the first insulating layer (3) forms the device (10), in which after the second conductive layer (5) deposited, the second insulating layer (4) is removed by means of an etching agent which is selective with respect to the material of the second conductive layer (5). According to the invention for the first material and the second material materials are selected which are only limitedly selectively etchable with respect to each other and before depositing the second insulating layer (4) a further layer (6) is provided on top of the first insulating layer (3) of a further material that is selectively etchable with respect to the first material. In this way a silicon oxide and a silicon nitride may be applied for the insulating layers (3, 4) and thus the method according to the invention is very compatible with current IC processes. The second insulating layer (4) is preferably removed locally by etching, then the further layer (6) is completely removed by etching and, finally, the second insulating layer (4) is completely removed by etching.

Abstract translation: 本发明涉及一种制造微机电器件（10）的方法，其中连续地沉积在其上形成有电极（2A）的第一导电层（2）的基板（1）上，第一电绝缘层 （3），与第一材料不同的第二材料的第二电绝缘层（4）和形成有与第一电极相对的第二电极（5A）的第二导电层（5），其中， 与第一电极（2A）和第一绝缘层（3）一起形成器件（10），其中在沉积第二导电层（5）之后，通过蚀刻去除第二绝缘层（4） 相对于第二导电层（5）的材料是选择性的。 根据本发明，选择第一材料和第二材料材料，其仅相对于彼此有限地可选择性地蚀刻，并且在沉积第二绝缘层（4）之前，另外的层（6）设置在第一绝缘体 层（3），其可相对于第一材料可选择性地蚀刻。 以这种方式，可以对绝缘层（3,4）施加氧化硅和氮化硅，因此根据本发明的方法与当前的IC工艺非常兼容。 优选通过蚀刻局部地去除第二绝缘层（4），然后通过蚀刻完全去除另外的层（6），最后通过蚀刻完全去除第二绝缘层（4）。