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公开(公告)号:US09715350B2
公开(公告)日:2017-07-25
申请号:US15252414
申请日:2016-08-31
IPC分类号: G06F12/00 , G06F3/06 , G06F12/02 , G06F12/1036 , G06F12/1009 , G06F12/1027 , G06F9/44
CPC分类号: G06F3/0631 , G06F3/0604 , G06F3/0673 , G06F9/4401 , G06F9/4403 , G06F12/023 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F2212/1044 , G06F2212/657 , G06F2212/68
摘要: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.
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公开(公告)号:US09710393B2
公开(公告)日:2017-07-18
申请号:US14750982
申请日:2015-06-25
申请人: Intel Corporation
IPC分类号: G06F12/00 , G06F12/1009 , G06F12/1027 , G06F12/14 , G06F9/455 , G06F21/00
CPC分类号: G06F12/1009 , G06F9/45533 , G06F9/45558 , G06F12/1027 , G06F12/1483 , G06F21/00 , G06F21/53 , G06F2009/45583 , G06F2009/45587 , G06F2212/1024 , G06F2212/1052 , G06F2212/151 , G06F2212/651 , G06F2212/657 , G06F2212/68 , G06F2221/2141
摘要: Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page tables by virtual machine (VM) guest software through the manipulation of extended page tables. The system may include a translation look-aside buffer (TLB) to maintain a policy to lock one or more guest linear addresses (GLAs) to one or more allowable guest physical addresses (GPAs); a page walk processor to update the TLB based on the guest page tables; and a page table edit control (PTEC) module to: identify entries of the guest page tables that map GLAs associated with the policy to a first GPA; verify that the mapping conforms to the policy; and place the guest page table into one of a plurality of restricted accessibility states based on the verification, the restricted accessibility applied to the VM guests and to the page walk processor.
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公开(公告)号:US20170177239A1
公开(公告)日:2017-06-22
申请号:US15451884
申请日:2017-03-07
发明人: Tadashi ONO
IPC分类号: G06F3/06 , G06F12/122 , G06F12/128
CPC分类号: G06F12/1027 , G06F3/0607 , G06F3/0655 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F12/0875 , G06F12/1009 , G06F12/128 , G06F2212/68 , G06F2212/70 , G06F2212/7203
摘要: Provided is a memory device with improved memory region usage efficiency. The memory device includes flash memory including: a control information (FAT) region that stores FAT for a file and a user data (UD) region that stores UD; cache memory including a FAT cache region that stores all or part of the FAT; an I/F that receives a write command for writing one of the FAT and the UD; and a memory controller that determines whether write data to be written is the FAT or the UD based on an address included in the write command, and sets the size of the FAT cache region based on an update frequency or an update count for the address included in the write command for the write data determined to be the FAT by the determiner.
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公开(公告)号:US20170161207A1
公开(公告)日:2017-06-08
申请号:US15440556
申请日:2017-02-23
发明人: Charles E. Mari , Harris M. Morgenstern , Thomas F. Rankin , Peter J. Relson , Elpida Tzortzatos
IPC分类号: G06F12/1027 , G06F12/1009
CPC分类号: G06F3/0619 , G06F3/0659 , G06F3/0685 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/1009 , G06F12/1027 , G06F12/145 , G06F2212/1016 , G06F2212/1052 , G06F2212/60 , G06F2212/621 , G06F2212/657 , G06F2212/68
摘要: A memory system is configured for access by a plurality of computer processing units. An address lock bit is configured in a translation table of the memory system. The address lock supports both address lock shared and address lock exclusive functions. A storage manager of an operating system configured to obtain exclusive access to an entry in a DAT table either by obtaining an address space lock exclusive or obtaining an address space lock shared, and setting a lock bit in a DAT entry.
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公开(公告)号:US20170153985A1
公开(公告)日:2017-06-01
申请号:US15432307
申请日:2017-02-14
发明人: Tong CHEN , John Kevin O'BRIEN , Zehra Noman SURA
IPC分类号: G06F12/1027 , G06F12/1009
CPC分类号: G06F12/1027 , G06F8/65 , G06F8/751 , G06F9/4552 , G06F11/073 , G06F11/0772 , G06F11/0793 , G06F11/28 , G06F11/3632 , G06F12/1009 , G06F2212/1024 , G06F2212/65 , G06F2212/68 , G06F2212/684
摘要: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.
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公开(公告)号:US09666250B2
公开(公告)日:2017-05-30
申请号:US15000394
申请日:2016-01-19
申请人: Rambus Inc.
发明人: Ian Shaeffer
IPC分类号: G06F3/00 , G11C7/10 , G06F13/16 , G06F12/1009 , G06F12/1027
CPC分类号: G11C7/1048 , G06F12/1009 , G06F12/1027 , G06F13/16 , G06F13/1673 , G06F2212/657 , G06F2212/68 , G11C7/1072 , Y02D10/14
摘要: Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.
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公开(公告)号:US20170147342A1
公开(公告)日:2017-05-25
申请号:US15396576
申请日:2016-12-31
申请人: Intel Corporation
发明人: Kirk S. YAP , Gilbert M. WOLRICH , James D. GUILFORD , Vinodh GOPAL , Erdinc OZTURK , Sean M. GULLEY , Wajdi K. FEGHALI , Martin G. DIXON
IPC分类号: G06F9/30 , G06F9/38 , H04L9/06 , G06F12/0897 , G06F12/0875 , G06F12/1027 , G06F15/80 , G06F13/28
CPC分类号: G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30156 , G06F9/3802 , G06F9/384 , G06F9/3855 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F13/28 , G06F13/4068 , G06F13/4282 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , G06F2213/0026 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/122
摘要: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
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公开(公告)号:US20170147341A1
公开(公告)日:2017-05-25
申请号:US15396574
申请日:2016-12-31
申请人: Intel Corporation
发明人: Kirk S. YAP , Gilbert M. WOLRICH , James D. GUILFORD , Vinodh GOPAL , Erdinc OZTURK , Sean M. GULLEY , Wajdi K. FEGHALI , Martin G. DIXON
IPC分类号: G06F9/30 , G06F15/80 , H04L9/06 , G06F12/0875 , G06F12/1027 , G06F9/38 , G06F12/0897
CPC分类号: G06F21/602 , G06F9/30007 , G06F9/30036 , G06F9/30156 , G06F9/3016 , G06F9/384 , G06F9/3855 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F13/28 , G06F13/4068 , G06F13/4282 , G06F2212/452 , G06F2212/68 , G06F2213/0026 , G09C1/00 , H04L9/3239 , H04L2209/122
摘要: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
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公开(公告)号:US20170139840A1
公开(公告)日:2017-05-18
申请号:US14939063
申请日:2015-11-12
发明人: Matthias Klein , Marco Kraemer , Carsten Otte , Christoph Raisch
CPC分类号: G06F3/0644 , G06F3/0604 , G06F3/0673 , G06F9/5077 , G06F12/023 , G06F12/1009 , G06F12/1027 , G06F12/109 , G06F2212/1024 , G06F2212/1044 , G06F2212/1048 , G06F2212/656 , G06F2212/68 , G06F2212/684
摘要: In an approach for determining a physical address for object access in an object-based storage device (OSD) system, a processor divides a first data object into one or more partitions, including at least a first partition, and providing each partition for storage as individual stored objects in an OSD system. A processor adds a first entry in a page table, the first entry representing the first partition without an indication of a physical address. A memory management unit (MMU) of the OSD system receives a first request of the first partition. Responsive to receiving the first request of the first partition, a MMU identifies that the first entry of the page table represents the first partition. A MMU obtains a physical address of the first partition from one of a hardware component and a firmware component.
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公开(公告)号:US20170132149A1
公开(公告)日:2017-05-11
申请号:US15384625
申请日:2016-12-20
发明人: Joseph Zbiciak , Son H. Tran
IPC分类号: G06F12/1045 , G06F12/0862 , G06F12/1009 , G06F12/0897
CPC分类号: G06F12/1045 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3822 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要: A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.
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