公开(公告)号：US06900518B2

公开(公告)日：2005-05-31

申请号：US10694735

申请日：2003-10-29

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L21/329 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/12 ,  H01L29/20 ,  H01L29/24 ,  H01L29/32 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/00 ,  H01L23/58

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US06703684B2

公开(公告)日：2004-03-09

申请号：US09957547

申请日：2001-09-21

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L2900

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane (16) which has opposed top and bottom surfaces (15,17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件（10）具有包括漂移区（20）的有源区。 漂移区域（20）的至少一部分设置在具有相对的顶表面和底表面（15,17）的膜（16）中。 在一个实施例中，膜（16）的顶表面（15）具有直接或间接连接到其上的电端子，以允许跨越漂移区域（20）横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面（15），并且至少一个电端子直接或间接地连接到底表面（17），以允许垂直地施加电压跨越漂移 区域（20）。 在这些实施例的每一个中，膜（16）的底表面（17）不具有与其相邻定位的半导体衬底。

公开(公告)号：US20020041003A1

公开(公告)日：2002-04-11

申请号：US09957547

申请日：2001-09-21

Applicant: CAMBRIDGE SEMICONDUCTOR LIMITED

Inventor： Florin Udrea ,  Gehan Amaratunga

IPC: H01L029/00

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane (16) which has opposed top and bottom surfaces (15, 17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件（10）具有包括漂移区（20）的有源区。 漂移区域（20）的至少一部分设置在具有相对的顶表面和底表面（15,17）的膜（16）中。 在一个实施例中，膜（16）的顶表面（15）具有直接或间接连接到其上的电端子，以允许跨越漂移区域（20）横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面（15），并且至少一个电端子直接或间接地连接到底表面（17），以允许垂直地施加电压跨越漂移 区域（20）。 在这些实施例的每一个中，膜（16）的底表面（17）不具有与其相邻定位的半导体衬底。

公开(公告)号：US20230395701A1

公开(公告)日：2023-12-07

申请号：US17832306

申请日：2022-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Ming CHEN ,  Szu-Ying CHEN ,  Yen-Chun HUANG ,  Sen-Hong SYUE ,  Huicheng CHANG ,  Yee-Chia YEO

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L29/7812 ,  H01L29/7869

Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate. The dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode layer. Sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate structure. A silicon based liner is formed over the sidewall spacers. A first insulating layer is formed over the silicon based liner. The silicon based liner and the first insulating layer are thermally treating causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner. The dummy gate structure is removed to form a gate space in the first insulating layer. The gate space is formed with a high-k dielectric layer and a first conductive layer.

公开(公告)号：US20160315185A1

公开(公告)日：2016-10-27

申请号：US15198526

申请日：2016-06-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. Loechelt

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7809 ,  H01L21/28132 ,  H01L29/063 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813

Abstract: An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.

Abstract translation: 电子器件可以包括半导体层，覆盖半导体层的绝缘层和导电电极。 在一个实施例中，第一导电电极部件覆盖绝缘层，并且第二导电电极部件覆盖并与半导体层间隔开。 第二导电电极构件具有与第一端相对的第一端和第二端，其中半导体层和第一导电电极构件中的每一个比第二导电电极构件的第二端更靠近第二导电电极构件的第一端 导电电极部件。 在另一个实施例中，导电电极可以是大致L形的。 在另一实施例中，工艺可以包括形成第一和第二导电电极部件，使得它们彼此邻接。 第二导电电极部件可以具有侧壁间隔物的形状。

公开(公告)号：US09412862B2

公开(公告)日：2016-08-09

申请号：US13794020

申请日：2013-03-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gary H. Loechelt

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7809 ,  H01L21/28132 ,  H01L29/063 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813

Abstract: An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.

Abstract translation: 电子器件可以包括半导体层，覆盖半导体层的绝缘层和导电电极。 在一个实施例中，第一导电电极部件覆盖绝缘层，并且第二导电电极部件覆盖并与半导体层间隔开。 第二导电电极构件具有与第一端相对的第一端和第二端，其中半导体层和第一导电电极构件中的每一个比第二导电电极构件的第二端更靠近第二导电电极构件的第一端 导电电极部件。 在另一个实施例中，导电电极可以是大致L形的。 在另一实施例中，工艺可以包括形成第一和第二导电电极部件，使得它们彼此邻接。 第二导电电极部件可以具有侧壁间隔物的形状。

公开(公告)号：US20160005855A1

公开(公告)日：2016-01-07

申请号：US14852049

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Yu Chen

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/12 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7809 ,  H01L21/26513 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/78642

Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

Abstract translation: 横向沟槽MOSFET包括埋在衬底中的绝缘层，衬底中的主体区域，衬底中的隔离区域，身体区域上的第一漏极/源极区域，衬底中的第二漏极/源极区域，其中， 第一漏极/源极区域和第二漏极/源极区域在隔离区域的相对侧上，漂移区域包括形成在第二漏极/源极区域和绝缘层之间的第一掺杂密度的第一漂移区域，其中第一 漂移区域包括由隔离区围绕的上部和形成在隔离区和绝缘层之间的第二掺杂浓度的下部和第二漂移区，其中第二漂移区的高度等于下部的高度 第一漂移区域的一部分。

公开(公告)号：US20150364597A1

公开(公告)日：2015-12-17

申请号：US14824491

申请日：2015-08-12

Applicant: Silanna Semiconductor U.S.A., Inc.

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

Abstract translation: 在具有第一表面，第二表面和背景掺杂的半导体层中形成垂直半导体器件。 在半导体层的第二表面形成掺杂到与背景相反的导电类型的第一掺杂区域。 在第一掺杂区域的内部，在半导体层的第二表面形成与背景相同导电类型的第二掺杂区域。 半导体层的一部分在第一表面被去除，暴露出新的第三表面。 第三掺杂区域形成在第三表面的半导体层的内部。 至少对第二掺杂区域（经由第二表面）和第三掺杂区域（经由新的第三表面）进行电接触。 以这种方式，可以在减薄的半导体或SOI层中制造垂直DMOS，IGBT，双极晶体管，晶闸管和其他类型的器件。

公开(公告)号：US08916930B2

公开(公告)日：2014-12-23

申请号：US13223603

申请日：2011-09-01

Applicant: Yuan-Shun Chang ,  Yi-Yun Tsai ,  Kao-Way Tu

Inventor： Yuan-Shun Chang ,  Yi-Yun Tsai ,  Kao-Way Tu

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/06 ,  H01L21/74 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7809 ,  H01L21/74 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7812 ,  H01L29/7813

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Abstract translation: 提供了一种在轻掺杂衬底上的沟槽功率半导体器件。 该器件具有基极，至少包括栅极沟槽，多个第一重掺杂区域，体区域，源极掺杂区域，接触窗口，第二重掺杂区域和金属层的多个沟槽。 沟槽形成在基部。 第一重掺杂区域分别在沟槽下方并且与具有轻掺杂区域的相应沟槽的底部间隔开。 体区域包围沟槽并且以预定距离远离第一重掺杂区域。 源极掺杂区域位于体区的上部。 接触窗口与基座的边缘相邻。 第二重掺杂区域在由用于电连接第二重掺杂区域的金属层填充的接触窗口的下方。

公开(公告)号：US08871573B2

公开(公告)日：2014-10-28

申请号：US13547339

申请日：2012-07-12

Applicant: Franz Hirler ,  Andreas Meiser

Inventor： Franz Hirler ,  Andreas Meiser

IPC: H01L21/336 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/732 ,  H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/732 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42304 ,  H01L29/42372 ,  H01L29/66272 ,  H01L29/66295 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer-stack having a main horizontal surface, an opposite surface, a buried dielectric layer, a semiconductor wafer extending from the buried dielectric layer to the main horizontal surface, and a handling wafer extending from the buried dielectric layer to the opposite surface; etching a deep vertical trench into the semiconductor wafer at least up to the buried dielectric layer, wherein the buried dielectric layer is used as an etch stop; forming a vertical transistor structure comprising forming a first doped region in the semiconductor wafer; forming a first metallization on the main horizontal surface in ohmic contact with the first doped region; removing the handling wafer to expose the buried dielectric layer; and masked etching of the buried dielectric layer to partly expose the semiconductor wafer on a back surface opposite to the main horizontal surface.

Abstract translation: 提供一种形成半导体器件的方法。 该方法包括提供具有主水平表面，相对表面，埋入介质层，从掩埋介电层延伸到主水平表面的半导体晶片的晶片堆叠，以及从掩埋介电层延伸到 对面 将深的垂直沟槽蚀刻到至少直到埋入的介电层的半导体晶片内，其中埋入的介电层用作蚀刻停止层; 形成垂直晶体管结构，包括在半导体晶片中形成第一掺杂区; 在所述主水平表面上与所述第一掺杂区域欧姆接触形成第一金属化; 去除所述处理晶片以暴露所述埋入的介电层; 以及掩埋的介电层的掩模蚀刻以在与主水平表面相对的背面部分地暴露半导体晶片。