公开(公告)号：US09130063B2

公开(公告)日：2015-09-08

申请号：US14496617

申请日：2014-09-25

申请人： Sanken Electric Co., LTD.

发明人： Hiroko Kawaguchi ,  Hiromichi Kumakura ,  Satoru Washiya ,  Toru Yoshie

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108 ,  H01L29/872 ,  H01L29/45 ,  H01L21/283 ,  H01L29/16

CPC分类号： H01L29/872 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/283 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47

摘要： A semiconductor device having a main electrode connected to a first semiconductor region and a second semiconductor layer on a semiconductor substrate so that a pn-junction diode is formed with the first semiconductor region being interposed and a Schottky barrier diode is formed with the second semiconductor layer being interposed on a surface of the semiconductor substrate, the semiconductor device includes a first electrode configured to ohmic-contact the first semiconductor region; a second electrode configured to Schottky-contact the second semiconductor layer and not having a portion directly contacting the first electrode; and a conductive reaction suppression layer to suppress a reaction between a material configuring the first electrode and a material configuring the second electrode are provided on the surface of the semiconductor substrate, and the main electrode is electrically connected to the first electrode and the second electrode.

摘要翻译： 一种半导体器件，其具有连接到第一半导体区域的主电极和在半导体衬底上的第二半导体层，使得形成有第一半导体区域的pn结二极管并且形成肖特基势垒二极管，其中第二半导体层 被插入在所述半导体衬底的表面上，所述半导体器件包括构造为与所述第一半导体区域欧姆接触的第一电极; 第二电极，其被配置为与所述第二半导体层肖特基接触，并且不具有直接接触所述第一电极的部分; 并且在半导体衬底的表面上设置用于抑制构成第一电极的材料和构成第二电极的材料之间的反应的导电反应抑制层，并且主电极与第一电极和第二电极电连接。

公开(公告)号：US20150236017A1

公开(公告)日：2015-08-20

申请号：US14184976

申请日：2014-02-20

申请人： Cree, Inc.

发明人： Fabian Radulescu

IPC分类号： H01L27/095 ,  H01L29/423 ,  H01L29/778 ,  H01L21/8232 ,  H01L29/16 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L29/812

CPC分类号： H01L27/095 ,  H01L21/8232 ,  H01L27/0605 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8128

摘要： A first dielectric layer including a first opening is provided on a first surface of a semiconductor layer. A second dielectric layer is provided on top of the first dielectric layer in the first opening. A first portion of the second dielectric layer is then removed, such that a second portion of the second dielectric layer remains in the first opening. The first dielectric layer is then removed, leaving only the second portion of the second dielectric layer on the surface of the semiconductor layer. An epitaxial layer or a base dielectric layer is grown on the exposed portions of the first surface of the semiconductor layer not covered by the second portion of the second dielectric layer. The second portion of the second dielectric layer is then removed to define one or more contact windows, and a contact metal is deposited in the one or more contact windows.

摘要翻译： 包括第一开口的第一电介质层设置在半导体层的第一表面上。 在第一开口中的第一电介质层的顶部上设置第二电介质层。 然后去除第二介电层的第一部分，使得第二介电层的第二部分保留在第一开口中。 然后去除第一介电层，仅在半导体层的表面上留下第二介电层的第二部分。 在半导体层的未被第二电介质层的第二部分覆盖的第一表面的暴露部分上生长外延层或基底电介质层。 然后去除第二介电层的第二部分以限定一个或多个接触窗口，并且接触金属沉积在一个或多个接触窗口中。

公开(公告)号：US20150137139A1

公开(公告)日：2015-05-21

申请号：US14574982

申请日：2014-12-18

申请人： Infineon Technologies Austria AG

发明人： Franz Hirler ,  Andreas Meiser

IPC分类号： H01L27/095 ,  H01L29/201 ,  H01L29/205 ,  H01L21/265 ,  H01L27/092 ,  H01L29/04 ,  H01L29/778 ,  H01L29/20 ,  H01L29/16

CPC分类号： H01L27/095 ,  H01L21/265 ,  H01L21/76283 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/045 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/78

摘要： A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

摘要翻译： 公开了一种半导体器件。 在一个实施例中，半导体器件包括两种不同的半导体材料。 两个半导体材料在公共平面中彼此相邻布置。

公开(公告)号：US08928410B2

公开(公告)日：2015-01-06

申请号：US13803792

申请日：2013-03-14

申请人： ACCO Semiconductor, Inc.

发明人： Alexandre G. Bracale ,  Denis A. Masliah

IPC分类号： H03F3/16 ,  H01L27/088 ,  H01L21/82 ,  H01L27/06 ,  H03F1/22 ,  H03F3/195 ,  H03F3/24 ,  H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H01L27/095 ,  H01L27/098

CPC分类号： H01L27/088 ,  H01L21/82 ,  H01L27/0617 ,  H01L27/095 ,  H01L27/098 ,  H03F1/0266 ,  H03F1/223 ,  H03F1/56 ,  H03F3/1935 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/387

摘要： Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

摘要翻译： 提供电子电路和方法用于各种应用，包括信号放大。 示例性电子电路包括MOSFET和共栅二极管配置的双栅极JFET。 双栅极JFET包括设置在通道上方和下方的顶部和底部门。 JFET的顶栅由信号控制，该信号取决于控制MOSFET栅极的信号。 JFET的底栅的控制可以取决于或不依赖于顶栅的控制。 MOSFET和JFET可以在不同尺寸（如栅极宽度）的同一衬底上实现为单独的组件。

公开(公告)号：US08878327B2

公开(公告)日：2014-11-04

申请号：US13730649

申请日：2012-12-28

申请人： Industrial Technology Research Institute

发明人： Cheng-Tyng Yen ,  Young-Shying Chen ,  Chien-Chung Hung ,  Chwan-Ying Lee

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L29/04 ,  H01L31/036 ,  H01L31/108 ,  H01L29/80 ,  H01L31/112 ,  H01L31/00 ,  H01L29/66 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/8725

摘要： A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate.

摘要翻译： 肖特基势垒器件包括半导体衬底，第一接触金属层，第二接触金属层和绝缘层。 半导体衬底具有第一表面，并且在第一表面上形成多个沟槽。 每个沟槽包括具有第一深度的第一凹部和具有第二深度的第二凹部。 第二凹部从第一表面向下延伸，同时第一凹部从第二凹部向下延伸。 第一接触金属层形成在第二凹部上。 第二接触金属层形成在两个相邻沟槽之间的第一表面上。 绝缘层形成在第一凹部上。 形成在第一接触金属层和半导体衬底之间的第一肖特基势垒大于形成在第二接触金属层和半导体衬底之间的第二肖特基势垒。

公开(公告)号：US08729664B2

公开(公告)日：2014-05-20

申请号：US13437273

申请日：2012-04-02

申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

IPC分类号： H01L29/15 ,  H01L23/52 ,  H01L29/47 ,  H01L27/095

CPC分类号： H01L29/0619 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.

摘要翻译： 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并从所述半导体衬底延伸穿过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

公开(公告)号：US08183659B2

公开(公告)日：2012-05-22

申请号：US12830135

申请日：2010-07-02

申请人： Mohammad Shafiqul Kabir

发明人： Mohammad Shafiqul Kabir

IPC分类号： H01L27/095

CPC分类号： B01J23/755 ,  B01J23/76 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/34 ,  C01B2202/36 ,  C23C16/04 ,  C23C16/26 ,  D01F9/08 ,  D01F9/127 ,  H01B1/04 ,  H01J1/304 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30469 ,  H01J2237/31786 ,  H01L21/76876 ,  H01L21/76885 ,  H01L23/53276 ,  H01L29/0676 ,  H01L51/0003 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512 ,  H01L2221/1089 ,  H01L2221/1094 ,  Y10S977/734 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/814 ,  Y10S977/842 ,  Y10S977/86

摘要： The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.

摘要翻译： 本发明提供在导电或绝缘基板上生长的纳米结构及其制造方法。 根据要求保护的方法生长的纳米结构适用于电子器件中的互连和/或散热器。

公开(公告)号：US08134219B2

公开(公告)日：2012-03-13

申请号：US13150831

申请日：2011-06-01

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC分类号： H01L29/808 ,  H01L29/0619 ,  H01L29/66143 ,  H01L29/66901 ,  H01L29/806 ,  H01L29/872

摘要： Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

摘要翻译： 通过以串联位于包括肖特基接触和第二端子的第一端子之间的第一导电类型的电流路径构建JFET来提供具有减小的漏电流和改善的击穿电压的改进的肖特基二极管。 电流通路是（i）在肖特基接触的基本上横向外侧的第二相对导电类型的多个基本上平行的手指区域之间，以及（ii）部分地位于第二导电类型的掩埋区域之下， 路径，哪些区域电耦合到第一端子和肖特基接触，哪个部分电耦合到第二端子。 当对第一端子和肖特基触点施加反向偏压时，电流路径在垂直或水平方向或两者上基本上被夹断，从而减小漏电流并提高器件的击穿电压。

公开(公告)号：US08129814B2

公开(公告)日：2012-03-06

申请号：US13085102

申请日：2011-04-12

申请人： Sameer Prakash Pendharkar ,  Eugen Pompiliu Mindricelu

发明人： Sameer Prakash Pendharkar ,  Eugen Pompiliu Mindricelu

IPC分类号： H01L27/095 ,  H01L29/792

CPC分类号： H01L27/0814 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0619 ,  H01L29/47 ,  H01L29/872

摘要： An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.

摘要翻译： 集成电路包括具有由n型半导体区域限定的阴极的肖特基二极管，由硅化钴区域限定的阳极和横向环形地环绕硅化钴区域的p型区域。 所得的p-n结在肖特基结下形成耗尽区，在反向偏压操作中减少穿过肖特基二极管的漏电流。 n +型接触区域由p型区域与第一硅化物区域横向分离，并且在n型接触区域中形成第二钴硅化物区域。 硅化区域由硅阻挡介电层中的开口限定。 电介质材料留在p型区域上。 p型区域可以与PMOS晶体管的源极/漏极区域同时形成。

公开(公告)号：US08044486B2

公开(公告)日：2011-10-25

申请号：US12653345

申请日：2009-12-11

申请人： François Hébert

发明人： François Hébert

IPC分类号： H01L27/095 ,  H01L29/93 ,  H01L29/861 ,  H01L31/107

CPC分类号： H01L29/872 ,  H01L29/402 ,  H01L29/66143 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current.

摘要翻译： 本发明公开了一种底阳极肖特基（BAS）二极管，其包括设置在半导体衬底的底表面上的阳极电极。 底阳极肖特基二极管还包括设置在半导体衬底中的深度处的沉降片掺杂剂区域，其基本上延伸到设置在半导体底表面上的阳极电极和由用作肖特基的埋地肖特基势垒金属覆盖的沉降弧掺杂区域 阳极。 BAS二极管进一步包括从阴极延伸到靠近半导体衬底的与肖特基势垒金属相对的顶表面的横向阴极区域，其中侧向阴极区域掺杂有与沉降弧掺杂区域相反的掺杂剂，并且与沉淀弧掺杂区域接合，由此 在施加正偏压时，通过横向阴极区和沉降弧掺杂区形成电流路径，并且在施加用于阻断泄漏电流的反向偏置电压时消耗阴极区的沉降掺杂区。