公开(公告)号：US20140183778A1

公开(公告)日：2014-07-03

申请号：US14108940

申请日：2013-12-17

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Jean-Philippe COLONNA ,  Christophe AUMONT ,  Stefan LANDIS

IPC: H01H1/00

CPC classification number: H01H1/00 ,  H01L21/76817 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/05552

Abstract: A method for making a conducting structure comprising steps of: forming on a given face of the support comprising at least one conducting element, at least one area for absorbing stresses based on a dielectric material, forming at least one aperture in said dielectric material by applying a mold on said dielectric material, said aperture being provided with inclined walls relatively to a normal to the main plane of said support, the bottom of said aperture revealing said conducting element, filling said aperture with a conducting material.

Abstract translation: 一种用于制造导电结构的方法，包括以下步骤：在包括至少一个导电元件的支撑体的给定面上形成至少一个用于吸收基于电介质材料的应力的区域，通过施加在所述电介质材料中形成至少一个孔 在所述电介质材料上的模具，所述孔相对于所述支撑件的主平面的法线设置有倾斜壁，所述孔的底部露出所述导电元件，用导电材料填充所述孔。

公开(公告)号：US20140176228A1

公开(公告)日：2014-06-26

申请号：US14134081

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

公开(公告)号：US20140170834A1

公开(公告)日：2014-06-19

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  STMicroelectronics S.A.

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140106529A1

公开(公告)日：2014-04-17

申请号：US14051174

申请日：2013-10-10

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Remi Beneyton

IPC: H01L29/66

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845

Abstract: A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (RTA) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure.

Abstract translation: 热退火流程包括以下步骤：在硅半导体结构上沉积金属或金属合金，执行快速热退火（RTA）型的第一退火以在硅半导体结构的一部分中产生富金相， 去除未反应的金属或金属合金，并在低于硅半导体结构中存在的硅材料的熔融温度的温度下进行第二退火作为毫秒退火。

公开(公告)号：US20140091451A1

公开(公告)日：2014-04-03

申请号：US14032618

申请日：2013-09-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Delpech ,  Eric Sabouret ,  Sebastien Gallois-Garreignot

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L23/562 ,  H01L21/50 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/02235 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/131 ,  H01L2924/014

Abstract: A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.

Abstract translation: 半导体器件可以包括邻近器件的顶表面的至少一个焊盘以及位于该至少一个焊盘下方的金属裂纹停止结构。 金属裂纹结构可以具有内封套和外封套，并且可以被配置为与至少一个焊盘垂直对准，使得至少一个焊盘的边缘在内包封和外包封之间。

公开(公告)号：US08656320B2

公开(公告)日：2014-02-18

申请号：US13937633

申请日：2013-07-09

Applicant: STMicroElectronics (Crolles 2) SAS

Inventor： Christian Gardin

IPC: G06F17/50 ,  G06K9/00 ,  G21K5/00 ,  G03F1/00 ,  G06F19/00 ,  G03F1/36 ,  G03F1/38

CPC classification number: G06F17/5081 ,  G03F1/0069 ,  G03F1/0092 ,  G03F1/30 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06K9/00 ,  G21K5/00

Abstract: A method for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set includes first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method includes a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.

Abstract translation: 一种从布置成形成初始掩模的一组初始掩模单元创建光刻掩模的方法。 该组包括在初始掩模的初始区域内具有共同的掩模元件的第一和第二初始掩模单元。 该方法包括创建第一修改屏蔽单元和包括OPC处理操作的第二修改屏蔽单元，比较第一修改屏蔽单元和第二修改屏蔽单元之间共同的掩模元件的位置，以及如果 比较结果大于阈值，创建包括初始区域上的光学邻近校正处理操作的新掩模区域，以及从新掩模区域创建光刻掩模。

公开(公告)号：US20140027886A1

公开(公告)日：2014-01-30

申请号：US14040270

申请日：2013-09-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel-Camille Bensahel ,  Yves Morand

IPC: H01L21/22 ,  H01L29/36

CPC classification number: H01L21/22 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/36 ,  H01L29/66659

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract translation: 半导体器件通过在半导体衬底内形成至少一个由具有基本上垂直于衬底厚度的方向上具有不均匀组成的材料形成的连续区域来制造。

公开(公告)号：US20250164680A1

公开(公告)日：2025-05-22

申请号：US18942211

申请日：2024-11-08

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Raphael MULIN ,  Olivier JEANNIN ,  Francois DENEUVILLE

IPC: G02B5/26 ,  G01J1/44 ,  G02B5/20 ,  G02B13/14

Abstract: The disclosure relates to an optoelectronic device comprising in a stack: one reflection polarizing filter, one phase-shifting element configured to add a π/4 phase shift in polarization, one active region, one reflector, so that the light radiation rays reflected by the reflector and passing through the phase-shifting element exhibit a new polarization phase-shifted by π/2 with respect to their initial polarization, the rays then being reflected anew by the polarizing filter in the direction of the active region.

公开(公告)号：US20240429934A1

公开(公告)日：2024-12-26

申请号：US18748787

申请日：2024-06-20

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  JUNIA ,  UNIVERSITE DE LILLE ,  UNIVERSITE POLYTECHNIQUE HAUTS-DE-FRANCE ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Antoine FRAPPÉ ,  Benoît LARRAS ,  Andreia CATHELIN ,  Soufiane MOURRANE

IPC: H03M1/12 ,  H03H17/00 ,  H03H17/06 ,  H03M1/06

Abstract: Device (1), for continuous-time energy calculation of an analog signal, comprising: a continuous-time analog-to-digital converter which is configured to convert the analog signal into a request signal (REQ), and a direction signal (DIR); at least one filtering unit (11), configured to output a filtered output signal (Fout), and comprising a delaying module (12) and a calculating module (15), connected to the delaying module (12) and configured calculate the filtered output signal (Fout). According to the invention, the device (1) further comprises: at least one pulse combiner (16), connected to the delaying module (12) and configured to output a combined request signal (CREQ); and at least one energy estimator (17), connected to the filtering unit (11) and to the pulse combiner (16), configured to compute a stored energy value (Aout) associated with each pulse of the combined request signal (CREQ).

公开(公告)号：US12143743B2

公开(公告)日：2024-11-12

申请号：US17372798

申请日：2021-07-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Lalanne ,  Pierre Malinge

IPC: H04N25/771 ,  H04N25/53 ,  H04N25/75

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.