公开(公告)号：US09306036B2

公开(公告)日：2016-04-05

申请号：US13953833

申请日：2013-07-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Michael Ganz

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L21/02362 ,  G06F17/505 ,  G06F2217/02 ,  H01L21/0217 ,  H01L27/0207 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

摘要： Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.

摘要翻译： 提供了使用氮化物间隔物来保护半导体器件（例如，鳍式场效应晶体管器件（FinFET））的方法。 具体地说，在FinFET器件的一个氧化物和一组鳍片之上形成一个氮化物间隔物，以减轻随后的处理过程中的损坏。 在阻挡层之前沉积氮化物间隔物，以在未被光致抗蚀剂覆盖的FinFET器件的开放区域中的一组栅极的顶部上保护氧化物。 每个栅极顶部的氧化物将保留在所有块层中，以在随后的源/漏外延层分层期间提供硬掩模保护。 此外，由光致抗蚀剂或该组栅极打开和未覆盖的翅片仍然被氮化物间隔物保护。 因此，防止由于暴露于抗蚀剂剥离处理的翅片的非晶化而引起的翅片侵蚀，从而提高了器件的产率。

公开(公告)号：US09257557B2

公开(公告)日：2016-02-09

申请号：US14282463

申请日：2014-05-20

申请人： GLOBALFOUNDRIES Inc.

发明人： David P. Brunco

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L21/823412 ,  H01L21/0245 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7849

摘要： Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

摘要翻译： 本发明的实施方案提供了具有应变松弛缓冲液的半导体结构及其制造方法。 应变松弛缓冲器设置在半导体衬底上。 在应变缓和缓冲器上，硅区域和硅锗区域彼此相邻设置。 硅或硅锗的附加区域提供量子阱隔离。

公开(公告)号：US09252203B2

公开(公告)日：2016-02-02

申请号：US14271515

申请日：2014-05-07

申请人： GLOBALFOUNDRIES Inc.

发明人： Hui Zang ,  Bingwu Liu

IPC分类号： H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

摘要翻译： 本发明的实施例提供改进的金属 - 绝缘体 - 金属（MIM）电容器。 在实施例中，通过在MIM电容器的底板下面形成通孔，导致金属化层或中间金属子层来减小串联电阻。 在实施例中，MIM电容器形成为波纹形状以增加板表面积，允许使用更厚的电介质，从而减轻漏电问题。

公开(公告)号：US09219002B2

公开(公告)日：2015-12-22

申请号：US14028724

申请日：2013-09-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Richard J. Carter ,  Hongliang Shen ,  Daniel Pham ,  Sruthi Muralidharan

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/308

CPC分类号： H01L21/76224 ,  H01L21/3081 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

摘要翻译： 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。

公开(公告)号：US09159794B2

公开(公告)日：2015-10-13

申请号：US14156745

申请日：2014-01-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Hong Yu ,  Jinping Liu

IPC分类号： H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

摘要翻译： 本发明的实施例提供了一种用于finFET的改进的接触形成方法。 在翅片上形成外延半导体区域。 接触蚀刻停止层（CESL）沉积在外延区域上。 氮化物 - 氧化物转换处理将氮化物CESL的一部分转化为氧化物。 使用选择性蚀刻工艺去除氧化物转化的部分，并且沉积与外延区域直接物理接触的填充金属。 在该过程期间，使外延区域的损耗（例如气蚀）最小化，导致finFET的接触改善。

公开(公告)号：US09129986B2

公开(公告)日：2015-09-08

申请号：US13929923

申请日：2013-06-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Hui Zang ,  Hyun-Jin Cho

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

摘要： Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

摘要翻译： 提供了替代金属门（RMG）设备中间隔倒角的方法。 具体地，半导体器件设置有由基板形成的一组翅片; 保形地沉积在该组翅片上的硅基层; 形成在硅基层上的蚀刻停止层（例如，氮化钛（TiN）），该蚀刻停止层对于硅，氧化物和氮化物中的至少一个是选择性的; 一组形成在衬底上的RMG结构; 沿着RMG结构集合中的每一个形成的一组隔离物，其中来自该组间隔物中的每一个的垂直材料层被选择性地移除到蚀刻停止层。 通过倒角每个侧壁间隔件，提供了用于后续功函（WF）金属沉积的较宽区域。 同时，每个晶体管沟道区域被蚀刻停止层（例如，TiN）覆盖，其在反应离子蚀刻期间维持原始栅极临界尺寸。

公开(公告)号：US09076868B1

公开(公告)日：2015-07-07

申请号：US14334953

申请日：2014-07-18

申请人： GLOBALFOUNDRIES Inc.

发明人： HaoCheng Tsai ,  Min-hwa Chi

IPC分类号： H01L21/762 ,  H01L29/78 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/0653 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/7846 ,  H01L29/7848

摘要： Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.

摘要翻译： 本发明的实施例提供了一种改进的浅沟槽隔离结构和制造方法。 浅沟槽隔离腔包括具有西格玛腔形状的上部区域和具有基本矩形横截面的下部区域。 下部区域填充有具有良好间隙填充性能的第一材料。 西格玛腔填充有具有良好的应力诱导性能的第二材料。 在一些实施例中，可以消除源极/漏极应力源空穴，同时由浅沟槽隔离结构提供的应力。 在其他实施例中，来自浅沟槽隔离结构的应力可以用于补偿或抵消来自相邻晶体管的源极/漏极应力区域的应力。 这使得能够精确地调谐通道应力以实现晶体管的期望的载流子迁移率。

公开(公告)号：US09018711B1

公开(公告)日：2015-04-28

申请号：US14056144

申请日：2013-10-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

摘要： Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

摘要翻译： 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

公开(公告)号：US08841140B2

公开(公告)日：2014-09-23

申请号：US11750567

申请日：2007-05-18

申请人： Tobias Letz ,  Matthias Lehr ,  Joerg Hohage ,  Frank Kuechenmeister

发明人： Tobias Letz ,  Matthias Lehr ,  Joerg Hohage ,  Frank Kuechenmeister

IPC分类号： C12Q1/70 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/3192 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05099

摘要： By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be “simulated,” thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity by omitting the deposition and patterning of the terminal metal layer stack.

摘要翻译： 通过确定用于形成凸块结构的钝化层堆叠的至少一个表面特性，终端金属层堆叠的沉积和图案化之后的情况可以“模拟”，从而提供使用公认的凸块制造技术的潜力 同时通过省略端子金属层堆叠的沉积和图案化显着地降低了工艺复杂性。

公开(公告)号：US11309220B2

公开(公告)日：2022-04-19

申请号：US15676005

申请日：2017-08-14

申请人： GLOBALFOUNDRIES INC.

发明人： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78

摘要： A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.