公开(公告)号：US20120198406A1

公开(公告)日：2012-08-02

申请号：US13422566

申请日：2012-03-16

Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Abstract translation: 一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

公开(公告)号：US20120007229A1

公开(公告)日：2012-01-12

申请号：US12832732

申请日：2010-07-08

Applicant: Gerald K. Bartley ,  David R. Motschman ,  Kamal K. Sikka ,  Jamil A. Wakil ,  Xiaojin Wei ,  Jiantao Zheng

Inventor： Gerald K. Bartley ,  David R. Motschman ,  Kamal K. Sikka ,  Jamil A. Wakil ,  Xiaojin Wei ,  Jiantao Zheng

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/49827 ,  H01L23/055 ,  H01L23/14 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/433 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/3003 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/3303 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/167 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.

Abstract translation: 提供了一个管芯堆叠封装，包括一个基板，一堆计算部件，至少一个与该堆叠热交换的热板，以及一个支撑在基板上的盖子，以围绕堆叠和至少一个热板，从而 限定从所述计算部件之一经由所述至少一个热板和联接到所述盖的表面和所述至少一个热板的翅片延伸到所述盖的第一热传递路径，以及从所述至少一个热板延伸的第二传热路径 计算组件之一到盖表面而不通过至少一个热板。

公开(公告)号：US08037272B2

公开(公告)日：2011-10-11

申请号：US12053131

申请日：2008-03-21

Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

IPC: G06F13/18

CPC classification number: G06F13/1689 ,  G06F13/1684

Abstract: A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.

Abstract translation: 为包含用于从外部源接收存储器访问命令的接口的存储器模块提供设计结构，其中接口的第一部分以第一总线频率接收存储器访问数据，并且接口的第二部分接收存储器访问数据 在第二个不同的总线频率。 优选地，存储器模块包含第二接口，用于重新传输也以双频操作的存储器访问数据。 存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。 优选地，存储器模块具有多模式操作，其中之一支持用于接收和重新传送数据访问命令的不同部分的双速总线，另一个支持常规的菊花链。

公开(公告)号：US20110238879A1

公开(公告)日：2011-09-29

申请号：US12731320

申请日：2010-03-25

Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/161 ,  Y02D10/14

Abstract: Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.

Abstract translation: 用于最佳地将存储器件放置在计算机系统内的方法和装置。 存储器控制器可以包括被配置为检索连接到其上的多个存储器件的一个或多个性能度量的电路。 基于性能度量和用于放置存储器设备的一个或多个预定义规则，电路可以确定系统中存储器件的最佳布局。

公开(公告)号：US07701244B2

公开(公告)日：2010-04-20

申请号：US12181367

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

IPC: H03K19/00

CPC classification number: G06F21/86 ,  G06F21/75 ,  H01L23/57 ,  H01L2224/32225

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract translation: 检测微芯片篡改的集成电路组件和相关联的方法可以包括与导电层电连通的多个连接。 防御性电路可能会阻止微芯片的分析，其中连接不再连接到导电层。 防御性电路可以类似地启动，其中连接不想与导电层电连通的连接是连接的。

公开(公告)号：US07667487B2

公开(公告)日：2010-02-23

申请号：US11971966

申请日：2008-01-10

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H03K19/173

CPC classification number: G06F1/26

Abstract: A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.

Abstract translation: 电路组件包括功能芯片和第一电容器。 功能芯片包括第一逻辑岛和第二逻辑岛。 第一电容器被配置为选择性地耦合（例如，在不同的时间）耦合到第一逻辑岛的第一电源端子和第二逻辑岛的第二电源端子。

公开(公告)号：US20090179669A1

公开(公告)日：2009-07-16

申请号：US11971966

申请日：2008-01-10

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H03K19/0175 ,  G06F1/26

CPC classification number: G06F1/26

Abstract: A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.

Abstract translation: 电路组件包括功能芯片和第一电容器。 功能芯片包括第一逻辑岛和第二逻辑岛。 第一电容器被配置为选择性地耦合（例如，在不同的时间）耦合到第一逻辑岛的第一电源端子和第二逻辑岛的第二电源端子。

公开(公告)号：US20090079060A1

公开(公告)日：2009-03-26

申请号：US11860226

申请日：2007-09-24

Applicant: GERALD K. BARTLEY ,  Darryl L. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： GERALD K. BARTLEY ,  Darryl L. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H01L23/15 ,  H01L21/98

CPC classification number: H01L21/563 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81365 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/0001 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2224/13099

Abstract: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole.

Abstract translation: 制造集成电路封装的方法包括在集成电路中形成通孔并将包含集成电路的管芯组装在载体上，使得管芯机械地和电连接到载体上。 此后，通过通孔将底部填充材料分配在模具和载体之间。

公开(公告)号：US20090058425A1

公开(公告)日：2009-03-05

申请号：US11848652

申请日：2007-08-31

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G01R31/02

CPC classification number: G01R31/2808 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/09063

Abstract: An apparatus for testing electrical continuity of a surface mounted (SMT) electrical board includes: a printed wiring board having a first surface and an opposite second surface; a conductive signal line disposed on each of the first and second surfaces of the printed wiring board; an electrical component disposed on and electrically connected to the conductive signal line on the first surface; and a through hole extending through the printed wiring board and the conductive signal line on the second surface of the printed wiring board exposing a surface side of the conductive signal line facing the first surface of the printed wiring board. The through hole is unplated in an inside bore defining the through hole and the through hole allows direct access to the conductive signal line on the first surface to test continuity of the conductive signal line on the first surface connected to the electrical component from the second surface of the printed wiring board.

Abstract translation: 一种用于测试表面安装（SMT）电气板的电气连续性的装置包括：具有第一表面和相对的第二表面的印刷线路板; 布置在所述印刷电路板的所述第一表面和所述第二表面中的每一个上的导电信号线; 设置在第一表面上并电连接到第一表面上的导电信号线的电气部件; 以及延伸穿过印刷线路板的通孔和印刷线路板的第二表面上的导电信号线，其暴露导电信号线的面对印刷线路板的第一表面的表面侧。 在限定通孔的内孔中没有通孔，并且通孔允许直接进入第一表面上的导电信号线，以测试从第二表面连接到电气部件的第一表面上的导电信号线的连续性 的印刷线路板。

公开(公告)号：US07492662B2

公开(公告)日：2009-02-17

申请号：US11688897

申请日：2007-03-21

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Philip R. Germann ,  William P. Hovis

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

Abstract translation: 随机存取存储器件包括排列成行和列的各个存储器单元的阵列，每个存储器单元具有与其相关联的访问器件。 阵列的每行还包括与其相关联的多个N字线，其中N对应于阵列的独立可访问分区的数量，其中给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列进行信号通信的地址解码器逻辑被配置为接收多个行地址位，并且对于由行地址位标识的所请求行，确定要请求行中的N个分区中的哪一个被访问， 未被激活的选定行内的设备，但不在要访问的分区内。