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    CAAC IGZO Deposited at Room Temperature
    41.
    发明申请
    CAAC IGZO Deposited at Room Temperature 审中-公开
    CAAC IGZO在室温下沉积

    公开(公告)号：US20150279674A1

    公开(公告)日：2015-10-01

    申请号：US14511475

    申请日：2014-10-10

    Applicant: Intermolecular, Inc.

    Inventor： Seon-Mee Cho ,  Sang Lee ,  Minh Huu Le

    IPC: H01L21/02 ,  H01L29/786 ,  H01L29/04 ,  C23C14/14

    CPC classification number: H01L21/02631 ,  C23C14/0036 ,  C23C14/086 ,  C23C14/352 ,  C23C14/562 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/045 ,  H01L29/66969 ,  H01L29/7869

    Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The third target includes a compound of indium oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, when deposited at room temperature, without the need of a subsequent anneal treatment.

    Abstract translation: 使用共溅射技术使用PVD沉积In-Ga-Zn-O膜。 膜在包括氧和氩的气氛中沉积。 约300℃的加热器设定值导致衬底温度为约165℃。一个靶包括In，Ga，Zn和O的合金，原子比为In：Ga：Zn为约1:1:1的原子比。 第二靶标包括氧化锌的化合物。 第三靶包括氧化铟的化合物。 当在室温下沉积时，膜以沉积状态呈现c轴对准的结晶（CAAC）相，而不需要随后的退火处理。

    Ultra-Low Resistivity Contacts
    43.
    发明申请
    Ultra-Low Resistivity Contacts 审中-公开
    超低电阻率触点

    公开(公告)号：US20150255332A1

    公开(公告)日：2015-09-10

    申请号：US14721248

    申请日：2015-05-26

    Applicant: Intermolecular, Inc.

    Inventor： Khaled Ahmed

    IPC: H01L21/768 ,  H01L21/66

    CPC classification number: H01L21/76864 ,  H01L21/02005 ,  H01L21/02104 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/14 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14698 ,  H01L29/1606 ,  H01L29/41 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786

    Abstract: Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10−9 Ω·cm2.

    Abstract translation: 公开了半导体器件的接触件及其制造方法。 一种方法包括在半导体上形成第一层，第一层包括一种或多种金属; 在所述第一层上形成第二层，所述第二层包含所述一种或多种金属，氮和氧; 以及加热所述第一层和所述第二层，使得氧从所述第二层迁移到所述第一层中，并且所述第一层在加热后包括亚化学计量的金属氧化物。 示例性实施例在第一层中使用诸如Ti之类的过渡金属。 在加热之后，在金属氮化物导体和半导体之间存在约2.5nm厚度的亚化学计量氧化层。 比接触电阻率小于约7×10-9＆OHgr·cm2。

    Silver based conductive layer for flexible electronics
    44.
    发明授权
    Silver based conductive layer for flexible electronics 有权
    用于柔性电子元件的银基导电层

    公开(公告)号：US09121100B2

    公开(公告)日：2015-09-01

    申请号：US13715477

    申请日：2012-12-14

    Applicant: Intermolecular Inc.

    Inventor： Mohd Fadzli Anwar Hassan ,  Guowen Ding ,  Minh Huu Le ,  Minh Anh Anh Nguyen ,  Zhi-Wen Wen Sun ,  Guizhen Zhang

    IPC: C23C28/00 ,  C23C30/00 ,  H01L51/52 ,  H01L51/00

    CPC classification number: H05K1/092 ,  C23C28/42 ,  C23C30/00 ,  H01L51/0097 ,  H01L51/5234 ,  H05K1/0274 ,  Y10T428/265

    Abstract: Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1.5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack to have an improved ductility property.

    Abstract translation: 制造导电叠层的方法包括形成夹在两层透明导电氧化物（例如氧化铟锡（ITO））之间的掺杂或合金化的银层。 掺杂的银或银合金层可以是薄的，例如在1.5至20nm之间，因此可以是透明的。 掺杂的银或银合金可以提供改善的延展性，允许导电叠层可弯曲。 透明导电氧化物层也可以是薄的，允许导电叠层具有改善的延展性。

    Modular Flow Cell and Adjustment System
    45.
    发明申请
    Modular Flow Cell and Adjustment System 审中-公开
    模块化流通池和调整系统

    公开(公告)号：US20150235875A1

    公开(公告)日：2015-08-20

    申请号：US14701861

    申请日：2015-05-01

    Applicant: Intermolecular, Inc.

    Inventor： Kurt Weiner ,  Aaron Francis ,  Ken Williams

    IPC: H01L21/67 ,  B01J19/00 ,  H01L21/687

    CPC classification number: H01L21/6715 ,  B01J19/0046 ,  B01J2219/00351 ,  B01J2219/00481 ,  B01J2219/00585 ,  H01L21/67028 ,  H01L21/67051 ,  H01L21/6719 ,  H01L21/68778

    Abstract: A combinatorial processing system having modular dispense heads is provided. The modular dispense heads are disposed on a rail system enabling an adjustable pitch of the modular dispense heads for the combinatorial processing. The modular dispense heads are configured so that sections of the modular dispense heads are detachable in order to accommodate various processes through a first section without having to completely disconnect and re-connect facilities to a second section.

    Abstract translation: 提供了具有模块化分配头的组合处理系统。 模块化分配头设置在轨道系统上，使得用于组合处理的模块化分配头的可调节距。 模块化分配头被配置为使得模块化分配头的部分可拆卸以便通过第一部分适应各种过程，而不必完全断开并将设备重新连接到第二部分。

    Method of depositing films with narrow-band conductive properties
    48.
    发明授权
    Method of depositing films with narrow-band conductive properties 有权
    沉积窄带导电性能的方法

    公开(公告)号：US09105704B2

    公开(公告)日：2015-08-11

    申请号：US13722931

    申请日：2012-12-20

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L21/3065 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/768

    CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/3105 ,  H01L21/76823 ,  H01L21/76826

    Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

    Abstract translation: 具有窄杂质导带的导电材料可以减少高能量激发的数量，并且可以通过一系列等离子体处理来制备。 例如，电介质层可以暴露于第一等离子体环境以形成空位，并且随后将空位形成的电介质层暴露于第二等离子体环境以用替代杂质填充空位。

    Methods for reproducible flash layer deposition
    49.
    发明授权
    Methods for reproducible flash layer deposition 有权
    可重复闪蒸层沉积的方法

    公开(公告)号：US09105646B2

    公开(公告)日：2015-08-11

    申请号：US13731548

    申请日：2012-12-31

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/02 ,  H01L49/02

    CPC classification number: H01L28/56 ,  H01L28/65 ,  H01L28/75

    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

    Abstract translation: 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

    Method and system of improved uniformity testing
    50.
    发明授权
    Method and system of improved uniformity testing 有权
    改进均匀性测试的方法和系统

    公开(公告)号：US09105563B2

    公开(公告)日：2015-08-11

    申请号：US13713421

    申请日：2012-12-13

    Applicant: Intermolecular, Inc.

    Inventor： Charlene Chen ,  Tony P. Chiang ,  Chi-I Lang ,  Yun Wang

    IPC: G01N21/59 ,  H01L21/66 ,  H01L29/16 ,  H01L21/02

    CPC classification number: H01L22/20 ,  G01N21/59 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/0262 ,  H01L22/12 ,  H01L29/1606

    Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

    Abstract translation: 一种方法和系统包括第一衬底和第二衬底，每个衬底在光的预定波长处包括预定的基线透射率值，第一衬底上的处理区域通过组合地改变材料，工艺条件，单元工艺中的至少一个和 与所述石墨烯生产相关联的工艺序列，对所述第一衬底上的所述经处理区域执行第一表征测试以产生第一结果，通过改变材料，工艺条件，单位过程中的至少一种以组合方式处理第二衬底上的区域， 以及基于第一表征测试的第一结果与石墨烯生产相关联的处理顺序，对第二衬底上的经处理区域执行第二表征测试以产生第二结果，以及确定第一衬底和第二衬底中的至少一个 基板满足预定的质量阈值 基于第二个结果。

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