公开(公告)号：US06824666B2

公开(公告)日：2004-11-30

申请号：US10059822

申请日：2002-01-28

Applicant: Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Muhammad Atif Malik ,  Sivakami Ramanathan ,  Girish A. Dixit ,  Robin Cheung

Inventor： Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Muhammad Atif Malik ,  Sivakami Ramanathan ,  Girish A. Dixit ,  Robin Cheung

IPC: C23C2800

CPC classification number: H01L21/76843 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1831 ,  C23C18/28 ,  C23C18/30 ,  C23C18/38 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76877 ,  H01L2221/1089 ,  Y10S428/936

Abstract: An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.

Abstract translation: 一种沉积包含至少一种选自贵金属，半贵金属，其合金及其组合的金属的催化剂层的装置和方法，其形成在基板上形成的亚微米特征。 贵金属的实例包括钯和铂。 半贵金属的实例包括钴，镍和钨。 可通过无电沉积，电镀或化学气相沉积来沉积催化层。 在一个实施方案中，催化层可以沉积在特征中以用作随后沉积的导电材料的阻挡层。 在另一个实施方案中，催化剂层可以沉积在阻挡层上。 在另一个实施方案中，催化层可以沉积在沉积在阻挡层上的种子层上，以充当种子层中任何不连续性的“贴片”。 一旦沉积了催化层，可以在催化剂层上沉积诸如铜的导电材料。 在一个实施例中，导电材料通过无电沉积沉积在催化剂层上。 在另一个实施方案中，导电材料通过无电沉积然后电镀或随后进行化学气相沉积沉积在催化剂层上。 在另一个实施例中，导电材料通过电镀或化学气相沉积沉积在催化层上。

公开(公告)号：US06797620B2

公开(公告)日：2004-09-28

申请号：US10124095

申请日：2002-04-16

Applicant: John S. Lewis ,  Srinivas Gandikota ,  Sivakami Ramanathan ,  Girish Dixit ,  Robin Cheung ,  Fusen Chen

Inventor： John S. Lewis ,  Srinivas Gandikota ,  Sivakami Ramanathan ,  Girish Dixit ,  Robin Cheung ,  Fusen Chen

IPC: H01L2144

CPC classification number: H01L21/2855 ,  H01L21/76879

Abstract: A method and apparatus is provided for filling apertures formed in a substrate surface by depositing materials that selectively inhibit or limit the formation or growth of subsequent layers used to fill an aperture. In one aspect, a method is provided for processing a substrate including providing a substrate having a field and apertures formed therein, wherein the apertures each have a bottom and sidewalls, depositing a seed layer on the bottom and sidewalls of the apertures, depositing a growth-inhibiting layer on at least one of the field of the substrate or an upper portion of the sidewalls of the apertures, and depositing a conductive layer on the growth-inhibiting layer and the seed layer. Deposition of the growth-inhibiting layer improves fill of the aperture from the bottom of the aperture up to the field of the substrate.

Abstract translation: 提供了一种方法和装置，用于通过沉积选择性地抑制或限制用于填充孔的后续层的形成或生长的材料来填充形成在衬底表面中的孔。 在一个方面，提供了一种用于处理衬底的方法，包括提供具有形成在其中的场和孔的衬底，其中每个孔具有底部和侧壁，在孔的底部和侧壁上沉积种子层，沉积生长 在衬底的场中的至少一个或孔的侧壁的上部中的至少一个上的抑制层，并且在生长抑制层和种子层上沉积导电层。 生长抑制层的沉积改善了孔的填充，从孔的底部到基底的场。

公开(公告)号：US06572010B2

公开(公告)日：2003-06-03

申请号：US09880185

申请日：2001-06-12

Applicant: Yezdi N. Dordi ,  Robin Cheung

Inventor： Yezdi N. Dordi ,  Robin Cheung

IPC: B23K120

CPC classification number: H01L21/67236 ,  B23K3/0623 ,  H01L21/67225 ,  H01L21/6723

Abstract: An integrated solder bump deposition method and apparatus that enables solder bumps to be lithographically formed on a substrate. The apparatus comprises a plurality of electrolyte cells, and etch/clean/passthrough station and a reflow chamber.

公开(公告)号：US6136163A

公开(公告)日：2000-10-24

申请号：US263126

申请日：1999-03-05

Applicant: Robin Cheung ,  Ashok Sinha ,  Avi Tepman ,  Dan Carl

Inventor： Robin Cheung ,  Ashok Sinha ,  Avi Tepman ,  Dan Carl

IPC: B65G49/07 ,  C25D7/12 ,  H01L21/00 ,  H01L21/02 ,  H01L21/288 ,  C25D17/00 ,  C25B9/00 ,  C25B15/00

CPC classification number: H01L21/6723 ,  C25D17/001 ,  H01L21/67098

Abstract: The present invention generally provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs rules and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, a rapid thermal anneal chamber disposed adjacent the loading station, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. One aspect of the invention provides a post electrochemical deposition treatment, such as a rapid thermal anneal treatment, for enhancing deposition results. Preferably, the electro-chemical deposition system includes a system controller adapted to control the electro-chemical deposition process and the components of the electro-chemical deposition system, including the rapid thermal anneal chamber disposed adjacent the loading station.

Abstract translation: 本发明通常提供一种电化学沉积系统，其被设计成具有可扩展以适应未来设计规则和间隙填充要求的柔性结构，并提供令人满意的吞吐量以满足其它处理系统的需求。 电化学沉积系统通常包括具有主机晶片传送机器人的主机，与主机连接设置的加载站，与加载站相邻设置的快速热退火室，与主机连接设置的一个或多个处理单元， 以及流体连接到所述一个或多个电处理单元的电解质供应。 本发明的一个方面提供了用于增强沉积结果的后电化学沉积处理，例如快速热退火处理。 优选地，电化学沉积系统包括适于控制电化学沉积过程和电化学沉积系统的部件的系统控制器，包括邻近加载站设置的快速热退火室。

公开(公告)号：US5837618A

公开(公告)日：1998-11-17

申请号：US906772

申请日：1997-08-06

Applicant: Steven Avanzino ,  Darrell Erb ,  Robin Cheung

Inventor： Steven Avanzino ,  Darrell Erb ,  Robin Cheung

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31612 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and substantially all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积绝缘材料的差的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后 间隙，停止非共形源材料的沉积，并且将可流动的绝缘材料（例如玻璃上的旋涂）涂覆在非共形绝缘材料上以填充剩余的间隙。 在蚀刻非共形和可流动的绝缘材料的表面之后，另外的绝缘层被沉积并平坦化到所需绝缘体的总厚度。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或 较低且基本上所有剩余的间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

公开(公告)号：US20140087073A1

公开(公告)日：2014-03-27

申请号：US14035567

申请日：2013-09-24

Applicant: Igor Constantin Ivanov ,  Robin Cheung

Inventor： Igor Constantin Ivanov ,  Robin Cheung

IPC: B05C9/06 ,  B05D1/38

CPC classification number: B05C9/06 ,  B05D1/38 ,  H01L21/67017 ,  H01L21/67126

Abstract: In various exemplary embodiments, a system and related method for processing substrates is provided. In one embodiment, a substrate processing system is provided that includes a substrate load module, a plurality of facilities modules, a plurality of process chambers, a substrate transfer module, at least one transfer gate to provide a contamination barrier between various ones of adjacent modules, and at least one gas impermeable shell to provide a controlled atmosphere within the substrate processing system.

Abstract translation: 在各种示例性实施例中，提供了一种用于处理基板的系统和相关方法。 在一个实施例中，提供了一种衬底处理系统，其包括衬底加载模块，多个设施模块，多个处理室，衬底转移模块，至少一个传输门，以在各个相邻模块之间提供污染屏障 ，以及至少一个气体不可渗透的外壳，以在基板处理系统内提供受控的气氛。

公开(公告)号：US08361560B2

公开(公告)日：2013-01-29

申请号：US13587774

申请日：2012-08-16

Applicant: Robin Cheung ,  Wen Zhong Kong

Inventor： Robin Cheung ,  Wen Zhong Kong

IPC: B05D1/02 ,  B05D1/18 ,  C23C18/42 ,  B32B15/01

CPC classification number: C23C18/54 ,  B32B15/018 ,  Y10T428/12875

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract translation: 一种用于在金属结构上浸镀铂金的铂电镀溶液。 浸渍铂电镀溶液不含还原剂。 电镀工艺不需要电（例如电流），并且不需要电极（例如阳极和/或阴极）。 该溶液包括铂源和包括草酸的络合剂。 该解决方案能够将铂浸入金属表面，金属基材或其至少一部分是金属的结构。 所得的铂镀层包括厚度不超过300埃的连续的铂薄膜层。 该溶液可用于包括但不限于珠宝，医疗装置，电子结构，微电子结构，MEMS结构，纳米尺寸或更小结构，用于化学和/或催化反应的结构（例如，催化转化器））的电镀制品， 和不规则形状的金属表面。

公开(公告)号：US08268667B2

公开(公告)日：2012-09-18

申请号：US13215895

申请日：2011-08-23

Applicant: Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

Inventor： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

IPC: H01L21/00

CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US20110315943A1

公开(公告)日：2011-12-29

申请号：US13225190

申请日：2011-09-02

Applicant: DARRELL RINERSON ,  JONATHAN BORNSTEIN ,  DAVID HANSEN ,  ROBIN CHEUNG ,  STEVEN W. LONGCOR ,  RENE MEYER ,  LAWRENCE SCHLOSS

Inventor： DARRELL RINERSON ,  JONATHAN BORNSTEIN ,  DAVID HANSEN ,  ROBIN CHEUNG ,  STEVEN W. LONGCOR ,  RENE MEYER ,  LAWRENCE SCHLOSS

IPC: H01L45/00 ,  B82Y99/00

CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the un-etched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层 导电金属氧化物（CMO）材料（例如PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域定位在CMO的未蚀刻层中的导电CMO区域附近，并且导电CMO区域设置在底部电极的上方并与底部电极接触并形成用于存储非易失性数据的存储元件 多个电导率分布（例如，表示存储的数据的电阻状态）。

公开(公告)号：US20110133147A1

公开(公告)日：2011-06-09

申请号：US12931773

申请日：2011-02-09

Applicant: Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

Inventor： Robin Cheung ,  Darrell Rinerson ,  Travis Byonghyop Oh ,  Jon Bornstein ,  David Hansen

IPC: H01L29/02

CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。