公开(公告)号：US09357659B2

公开(公告)日：2016-05-31

申请号：US14602645

申请日：2015-01-22

Applicant: Unimicron Technology Corporation

Inventor： Dyi-Chung Hu ,  Tzyy-Jang Tseng

IPC: H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/40 ,  H05K1/11 ,  H01L23/14 ,  H01L23/15 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias. As such, the first end surfaces of the conductive through-vias of the through-via interposer are electrically connected to the redistribution layer to thereby be electrically connected to electrode pads of a semiconductor chip having smaller pitches, while the second end surfaces of the conductive through-vias electrically connect with conductive vias of the built-up structure having larger pitches, thereby allowing the packaging substrate to be coupled with the semiconductor chip having high-density circuits.

Abstract translation: 提供具有嵌入式通孔插入器的封装衬底，其包括密封剂层，嵌入密封层中的通孔插入件，并且其中具有多个导电通孔，重分布层嵌入密封层中并形成在 所述通孔插入件与所述导电通孔的第一端面电连接，以及形成在所述密封层和所述通孔插入件上的积层结构，用于电连接所述导电通孔的第二端面 。 因此，通孔插入器的导电通孔的第一端面电连接到再分配层，从而与具有较小间距的半导体芯片的电极焊盘电连接，而导电的第二端面 通孔与具有较大间距的积层结构的导电通孔电连接，从而允许封装衬底与具有高密度电路的半导体芯片耦合。

公开(公告)号：US09024422B2

公开(公告)日：2015-05-05

申请号：US14046000

申请日：2013-10-04

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  I-Ta Tsai

IPC: H01L23/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L21/58 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.

Abstract translation: 具有嵌入式半导体元件的封装结构包括：具有活性表面的芯片，具有电极焊盘和与所述有源表面相对的无效表面; 第一绝缘保护层，其具有经由其有效表面安装在其上的芯片的芯片安装区域; 多个连接列，其设置在与所述电极焊盘对应的位置处的所述第一绝缘保护层中，并且经由焊锡凸块电连接到所述电极焊盘; 密封剂，其形成在所述第一绝缘保护层的一个表面上，所述第一绝缘保护层的芯片安装在其上，用于封装所述芯片; 以及形成在第一绝缘保护层和连接柱的另一个表面上的堆积结构。 由于包围物的抗弯曲性，防止了积层结构的翘曲。

公开(公告)号：US08999759B2

公开(公告)日：2015-04-07

申请号：US13900885

申请日：2013-05-23

Applicant: Unimicron Technology Corporation

Inventor： Kan-Jung Chia

IPC: H01L21/00 ,  H01L23/02 ,  H01L21/50 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00

CPC classification number: H01L21/50 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/185 ,  H05K3/0032 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.

Abstract translation: 一种用于制造具有嵌入式半导体元件的封装结构的方法，包括：提供具有相反的第一表面和第二表面的基底和至少穿过第一和第二表面的开口; 在所述第一表面上的所述开口的周边周围形成第一金属框架; 通过激光烧蚀在所述第一金属框架内部至少形成开口; 在开口处设置半导体芯片; 在所述第一和第二表面和所述芯片上形成第一电介质层; 在所述第一表面的所述第一介电层上形成第一布线层; 以及在第一介电层和第一表面的第一布线层上形成第一组合结构。 通过围绕预定开口区域的周边的第一金属框架精确地控制开口的形状，从而允许芯片被精确地嵌入在基板中。

公开(公告)号：US20140306340A1

公开(公告)日：2014-10-16

申请号：US14314242

申请日：2014-06-25

Applicant: Unimicron Technology Corporation

Inventor： Zhao-Chong Zeng

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.

Abstract translation: 具有嵌入式电子部件的封装结构包括：具有穿透其中的空腔的载体; 半导体芯片，其容纳在所述空腔中并且具有设置在其上的焊料凸块; 形成在所述载体和所述半导体芯片上以封装所述焊料凸块的电介质层; 形成在电介质层上的布线层; 形成在所述电介质层和所述布线层上的绝缘保护层; 以及形成在电介质层中的焊料材料和用于电连接布线层和焊料凸块的绝缘保护层，从而缩短半导体芯片和载体之间的信号传输路径，以避免信号损失。

公开(公告)号：US20140239490A1

公开(公告)日：2014-08-28

申请号：US13777097

申请日：2013-02-26

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Ying-Tung Wang

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73204

Abstract: A packaging substrate and a fabrication method thereof are disclosed. The packaging substrate includes: a substrate body having a plurality of first and second conductive pads formed on a surface thereof; a first insulating layer formed on the surface of the substrate body and having a plurality of first and second openings for respectively exposing the first and second conductive pads; a conductive layer formed on the first and second conductive pads and the first insulating layer around peripheries of the first and second conductive pads; a plurality of first and second conductive bumps formed on the conductive layer on the first and second conductive pads, respectively; a solder layer formed on the second conductive bumps; and a plurality of conductive posts formed on the first conductive bumps and having a width different from that of the first conductive bumps. The invention improves the fabrication efficiency.

Abstract translation: 公开了一种封装基板及其制造方法。 包装基板包括：基板主体，其具有形成在其表面上的多个第一和第二导电焊盘; 第一绝缘层，其形成在所述基板主体的表面上，并且具有用于分别暴露所述第一和第二导电焊盘的多个第一和第二开口; 形成在第一和第二导电焊盘上的导电层和围绕第一和第二导电焊盘周围的第一绝缘层; 分别形成在第一和第二导电焊盘上的导电层上的多个第一和第二导电凸块; 形成在所述第二导电凸块上的焊料层; 以及形成在所述第一导电凸块上并且具有与所述第一导电凸块的宽度不同的宽度的多个导电柱。 本发明提高了制造效率。

公开(公告)号：US20140201992A1

公开(公告)日：2014-07-24

申请号：US14097597

申请日：2013-12-05

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Yung-Ching Lin ,  Chih-Kuie Yang ,  Ta-Han Lin

IPC: H05K3/40

CPC classification number: H05K3/4647 ,  H05K1/185 ,  H05K2201/0358 ,  H05K2203/1189 ,  Y10T29/49155

Abstract: A method for fabricating a circuit board structure having at least an embedded electronic element is disclosed, which includes the steps of: providing a substrate and embedding at least an electronic element in the substrate with an active surface and a plurality of electrode pads of the electronic element exposed from a surface of the substrate; forming a plurality of conductive bumps on the electrode pads of the electronic element; and covering the surface of the substrate and the active surface of the electronic element with a dielectric layer and a metal layer stacked on the dielectric layer, wherein the conductive bumps penetrate the dielectric layer so as to be in contact with the metal layer, thereby simplifying the fabrication process, reducing the fabrication cost and saving the fabrication time.

Abstract translation: 公开了一种用于制造具有至少嵌入式电子元件的电路板结构的方法，其包括以下步骤：提供基板并且将基板中的至少一个电子元件嵌入到所述基板中，所述基板具有活性表面和所述电子元件的多个电极焊盘 元件从所述基板的表面露出; 在所述电子元件的电极焊盘上形成多个导电凸块; 并且用电介质层和层叠在电介质层上的金属层覆盖基板的表面和电子元件的有源面，其中，导体凸块穿透电介质层以与金属层接触，从而简化 制造工艺，降低制造成本，节省制造时间。

公开(公告)号：US20140117557A1

公开(公告)日：2014-05-01

申请号：US13966045

申请日：2013-08-13

Applicant: UNIMICRON TECHNOLOGY CORPORATION ,  INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yu-Hua CHEN ,  Wei-Chung LO ,  Dyi-Chung HU ,  Chang-Hong HSIEH

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: A package substrate and a method for forming the package substrate are disclosed. The package substrate includes an interposer having a plurality of conductive through vias and a first insulating layer formed on the sidewalls of the conductive through vias, a second insulating layer formed on one side of the interposer, and a plurality of conductive vias formed in the second insulating layer and electrically connected to the conductive through vias. By increasing the thickness of the first insulating layer, the face diameter of the conductive through vias can be reduced, and the layout density of the conductive through vias in the interposer can thus be increased.

Abstract translation: 公开了封装基板和形成封装基板的方法。 封装衬底包括具有多个导电通孔的插入件和形成在导电通孔的侧壁上的第一绝缘层，形成在插入件一侧上的第二绝缘层和形成在第二绝缘层中的多个导电通孔 绝缘层并电连接到导电通孔。 通过增加第一绝缘层的厚度，可以减小导电通孔的面直径，从而可以增加插入件中的导电通孔的布局密度。

公开(公告)号：US20140102777A1

公开(公告)日：2014-04-17

申请号：US14010250

申请日：2013-08-26

Applicant: Unimicron Technology Corporation ,  Industrial Technology Research Institute

Inventor： Yu-Hua CHEN ,  Wei-Chung LO ,  Dyi-Chung HU ,  Chang-Hong HSIEH

IPC: H05K3/40 ,  H05K1/11

CPC classification number: H05K3/4038 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/115 ,  Y10T29/49165

Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.

Abstract translation: 提供封装基板和制造封装基板的方法。 封装衬底可以包括具有至少一个导电通孔，形成在插入器的一侧上的光敏电介质层和至少一个形成在光敏电介质层中的导电通孔并且与导电通孔 通过。 通过具有高对准精度的光刻工艺，可以在感光介电层上形成至少一个具有极小直径的通孔，并与导电通孔对齐。 因此，导电通孔可以根据需要减小其直径，而不考虑与至少一个通孔的对准。 因此，插入件上的导电贯通孔的互连密度增加。

公开(公告)号：US20140027925A1

公开(公告)日：2014-01-30

申请号：US13845625

申请日：2013-03-18

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu ,  Ying-Chih Chan

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/115 ,  H05K2201/10378 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract translation: 提供了一种贯穿孔插入器，包括板体，形成在板体中的导电凝胶，以及布置在板体上的电路再分布结构。 导电性凝胶具有从板体的表面突出的一端，与其他结构（例如，封装基板或电路结构）接触的导电性凝胶的突出部的面积增加，从而加强 导电凝胶和插层的可靠性。

公开(公告)号：US20130230947A1

公开(公告)日：2013-09-05

申请号：US13865220

申请日：2013-04-18

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Shih-Ping Hsu ,  I-Ta Tsai

IPC: H01L21/58

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapsulant, the warpage of the built-up structure is prevented.

Abstract translation: 具有嵌入式半导体元件的封装结构包括：具有活性表面的芯片，具有电极焊盘和与所述有源表面相对的无效表面; 第一绝缘保护层，其具有经由其有效表面安装在其上的芯片的芯片安装区域; 多个连接列，其设置在与所述电极焊盘对应的位置处的所述第一绝缘保护层中，并且经由焊锡凸块电连接到所述电极焊盘; 密封剂，其形成在所述第一绝缘保护层的一个表面上，所述第一绝缘保护层的芯片安装在其上，用于封装所述芯片; 以及形成在第一绝缘保护层和连接柱的另一个表面上的堆积结构。 由于密封剂的抗弯曲性，防止了积层结构的翘曲。