公开(公告)号：US20090289097A1

公开(公告)日：2009-11-26

申请号：US12124844

申请日：2008-05-21

Applicant: Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: B23K1/00

CPC classification number: H01L21/67092 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/75 ,  H01L2224/75315 ,  H01L2224/7598 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A leveling-bonding method and an apparatus for performing the same are provided. The method includes providing a bond support for supporting a wafer; providing a bond head over the bond support; dispatching a foil over the wafer; placing the wafer on the bond support; and using the bond support and the bond head to apply a force on the foil and the wafer.

Abstract translation: 提供了一种调平方法及其执行装置。 该方法包括提供用于支撑晶片的接合支撑件; 在债券支持上提供债券头; 在晶片上调度箔片; 将晶片放置在粘合支撑件上; 并且使用粘合支撑件和结合头在箔和晶片上施加力。

公开(公告)号：US20090227047A1

公开(公告)日：2009-09-10

申请号：US12043714

申请日：2008-03-06

Applicant: Ku-Feng Yang ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Kewei Zuo

Inventor： Ku-Feng Yang ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Kewei Zuo

IPC: H01L21/00 ,  H01L21/306

CPC classification number: H01L21/67253 ,  H01L21/30604 ,  H01L21/6708 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for controlling substrate thickness. At least one etchant is dispensed from at least one dispenser to a plurality of different locations on a surface of a spinning substrate to perform etching. A thickness of the spinning substrate is monitored at the plurality of locations, so that the thickness of the substrate is monitored at each individual location while dispensing the etchant at that location. A respective amount of etching performed at each individual location is controlled, based on the respective monitored thickness at that location.

Abstract translation: 提供了一种控制基板厚度的方法。 至少一种蚀刻剂从纺丝衬底的表面从至少一个分配器分配到多个不同位置以进行蚀刻。 在多个位置监测纺丝衬底的厚度，从而在每个单独位置监测衬底的厚度，同时在该位置分配蚀刻剂。 基于在该位置处的相应监视的厚度来控制在每个单独位置执行的相应的蚀刻量。

公开(公告)号：US20090224405A1

公开(公告)日：2009-09-10

申请号：US12044008

申请日：2008-03-07

Applicant: Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu ,  Jung-Chih Hu

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu ,  Jung-Chih Hu

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a portion of the semiconductor substrate, followed forming an interconnection structure electrically connected with the contact plug and the via plug.

Abstract translation: 在具有形成在层间电介质（ILD）中的接触插塞的半导体衬底上进行通孔工艺，然后在ILD层中形成通孔以延伸穿过半导体衬底的一部分，然后电连接形成互连结构 与接触插头和通孔插头连接。

公开(公告)号：US20090142903A1

公开(公告)日：2009-06-04

申请号：US12054097

申请日：2008-03-24

Applicant: Chen-Hua Yu ,  Jui-Pin Hung ,  Weng-Jin Wu ,  Jean Wang ,  Wen-Chih Chiou

Inventor： Chen-Hua Yu ,  Jui-Pin Hung ,  Weng-Jin Wu ,  Jean Wang ,  Wen-Chih Chiou

IPC: H01L21/30 ,  B29C65/00

CPC classification number: H01L25/50 ,  H01L21/67051 ,  H01L24/28 ,  H01L24/75 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/8301 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01094 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/19042 ,  Y10T156/14 ,  H01L2924/00

Abstract: The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.

Abstract translation: 本公开提供了一种接合装置。 接合装置包括设计用于清洁芯片的清洁模块; 以及芯片到晶片接合室，其被配置为从所述清洁模块接收所述芯片并被设计用于将所述芯片接合到晶片。

公开(公告)号：US07466028B1

公开(公告)日：2008-12-16

申请号：US11873037

申请日：2007-10-16

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Hung-Jung Tu ,  Weng-Jin Wu

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Hung-Jung Tu ,  Weng-Jin Wu

IPC: H01L27/10 ,  H01L29/73 ,  H01L29/74 ,  H01L23/02 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a via defined in the substrate and extending from the first surface to the second surface; and a first plurality of contact structures on the first surface contacting the via. A cross section of each of the first plurality of contact structures parallel to the first surface has a first side and a second side, and a ratio of the longer side to the shorter side of the first side and the second side is more than about 2:1.

Abstract translation: 提供了一种用于三维集成电路的半导体器件结构。 半导体器件结构包括：具有第一表面和第二表面的衬底; 通孔，其限定在所述基板中并且从所述第一表面延伸到所述第二表面; 以及在所述第一表面上接触所述通孔的第一多个接触结构。 平行于第一表面的第一多个接触结构中的每一个的横截面具有第一侧和第二侧，并且第一侧和第二侧的长边与短边的比例大于约2 ：1。

公开(公告)号：US20080268614A1

公开(公告)日：2008-10-30

申请号：US11740178

申请日：2007-04-25

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L21/30

CPC classification number: H01L21/2007

Abstract: A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.

Abstract translation: 提供一种用于提供堆叠晶片配置的方法。 该方法包括将第一晶片接合到第二晶片。 将填料施加在沿着第一晶片和第二晶片的边缘形成的间隙中。 填充材料在减薄和运输过程中沿着边缘提供支撑以帮助减少开裂或碎裂。 可以固化填充材料以减少在施加填充材料时可能发生的任何起泡。 此后，可以通过研磨，等离子体蚀刻，湿蚀刻等来减薄第二晶片。 在本发明的一些实施例中，该过程可以重复多次以产生具有三个或更多个堆叠晶片的堆叠晶片配置。

公开(公告)号：US09299594B2

公开(公告)日：2016-03-29

申请号：US12844113

申请日：2010-07-27

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC: H01L21/67 ,  H01L21/683 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/6835 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/6836 ,  H01L22/12 ,  H01L22/26 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The embodiments described provide apparatus and methods for bonding wafers to carriers with the surface contours of plates facing the substrates or carriers are modified either by re-shaping, by using height adjusters, by adding shim(s), or by zoned temperature control. The modified surface contours of such plates compensate the effects that may cause the non-planarity of bonded substrates.

Abstract translation: 所描述的实施例提供了将晶片接合到载体上的装置和方法，其中面向基板或载体的板的表面轮廓通过重新成形，通过使用高度调节器，通过添加垫片或通过分区的温度控制来改变。 这种板的改进的表面轮廓补偿可能导致键合衬底的非平面性的影响。

公开(公告)号：US08853830B2

公开(公告)日：2014-10-07

申请号：US12178021

申请日：2008-07-23

Applicant: Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L23/538 ,  H01L25/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/768 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Abstract translation: 本发明提供一种制造用于半导体衬底叠层系统的半导体衬底结构的方法。 该方法包括半导体衬底，其包括前表面，背面，体层，互连层，其包括夹在导电层之间的多个金属间介电层，位于体层和互连之间的接触层 层，以及从本体层和接触层之间开始并终止于衬底背面的TSV结构。 TSV结构电耦合到互连层，并且TSV结构电耦合到背面的接合焊盘。

公开(公告)号：US08704375B2

公开(公告)日：2014-04-22

申请号：US12613417

申请日：2009-11-05

Applicant: Max Liu ,  Chao-Shun Hsu ,  Ya-Wen Tseng ,  Wen-Chih Chiou ,  Weng-Jin Wu

Inventor： Max Liu ,  Chao-Shun Hsu ,  Ya-Wen Tseng ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC: H01L23/48 ,  H01L29/417 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L29/4175 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L2223/6622 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.

Abstract translation: 公开了通过基板通过阻挡结构和方法。 在一个实施例中，半导体器件包括包括设置在隔离区域内的有源器件区域的第一衬底。 贯穿衬底通孔邻近有源器件区域并在第一衬底内设置。 缓冲层设置在穿过基底通孔的至少一部分周围，其中缓冲层设置在隔离区域和穿通基底通孔之间。

公开(公告)号：US08629565B2

公开(公告)日：2014-01-14

申请号：US13419078

申请日：2012-03-13

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Tsung-Ding Wang

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Tsung-Ding Wang

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/80006 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83

Abstract: A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer.

Abstract translation: 薄晶片保护装置包括具有多个半导体芯片的晶片。 晶片具有第一侧和相对的第二侧。 多个管芯在晶片的第一侧上方，多个管芯中的至少一个与多个半导体芯片中的至少一个接合。 晶片载体在晶片的第二面之上。 封装层在晶片的第一侧和多个管芯之上，并且封装层具有平坦的顶表面。 粘合带在封装层的平坦顶表面之上。