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41.发明授权Integrated circuit package system with multiple device units and method for manufacturing thereof 有权具有多个器件单元的集成电路封装系统及其制造方法公开(公告)号：US08203220B2
公开(公告)日：2012-06-19
申请号：US12797922
申请日：2010-06-10
CPC分类号： H01L23/49575 , H01L23/49541 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01027 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A method for manufacturing an integrated circuit package system includes: forming a first device unit, having first external interconnects arranged along a perimeter of the first device unit, and a second device unit, having second external interconnects arranged along a perimeter of the second device unit, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnects; encapsulating with an encapsulation covering the integrated circuit die, the first device unit, and the second device unit with both the first external interconnects and the second external interconnects partially exposed; and forming a partial encapsulation cut in the encapsulation electrically isolating the first external interconnects and the second electrical interconnects.
摘要翻译： 一种用于制造集成电路封装系统的方法，包括：形成具有沿着第一器件单元的周边布置的第一外部互连的第一器件单元和具有沿第二器件单元的周边布置的第二外部互连的第二器件单元 ，在阵列配置中; 在第一设备单元上安装集成电路管芯; 连接集成电路管芯和第一外部互连件; 封装了覆盖集成电路管芯，第一器件单元和第二器件单元的封装，其中第一外部互连和第二外部互连部分地被部分地暴露; 以及在所述封装中形成电隔离所述第一外部互连和所述第二电互连的部分封装切割。
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42.发明申请Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die 有权半导体器件和形成具有用于捕获半导体芯片的凹槽的基底的方法公开(公告)号：US20120126429A1
公开(公告)日：2012-05-24
申请号：US12953812
申请日：2010-11-24
CPC分类号： H01L24/14 , H01L21/4832 , H01L21/561 , H01L23/3107 , H01L23/3121 , H01L23/3128 , H01L23/49548 , H01L23/49582 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/10175 , H01L2224/16225 , H01L2224/16245 , H01L2224/26175 , H01L2224/2919 , H01L2224/32145 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/8114 , H01L2224/81203 , H01L2224/81385 , H01L2224/81815 , H01L2224/92247 , H01L2224/97 , H01L2225/06558 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/381 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2224/13099 , H01L2924/0665 , H01L2224/05099 , H01L2924/00 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.
摘要翻译： 半导体器件具有形成在基底基板的第一表面中的凹部的基底基板。 第一导电层形成在第一表面上并进入凹槽中。 在基底基板的第二表面上形成第二导电层。 第一半导体管芯安装到基底基板上，凸起部分设置在第一导电层的凹槽内。 第二半导体管芯安装到第一半导体管芯。 在第二半导体管芯和第一导电层之间的基底衬底的第一表面上形成接合线。 密封剂沉积在第一和第二半导体管芯和基底衬底上。 基底基板的一部分从第二导电层之间的第二表面移除到凹部，以形成用于凸块和接合线的电隔离的基底引线。
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公开(公告)号：US08120156B2
公开(公告)日：2012-02-21
申请号：US11307723
申请日：2006-02-17
IPC分类号： H01L23/02
CPC分类号： H01L25/03 , H01L24/73 , H01L25/0657 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06572 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides an integrated circuit package system with die on base package comprising forming a base package comprising, forming a substrate, mounting a first integrated circuit on the substrate, encapsulating the integrated circuit and the substrate with a molding compound, and testing the base package, attaching a bare die to the base package, connecting electrically the bare die to the substrate and encapsulating the bare die and the base package.
摘要翻译： 本发明提供了一种集成电路封装系统，其具有基底封装上的管芯，包括形成基底封装，其包括：形成衬底，将第一集成电路安装在衬底上，用模塑料封装集成电路和衬底，以及测试基底 封装，将裸芯片附接到基底封装，将裸裸片电连接到衬底并封装裸裸片和基底封装。
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公开(公告)号：US08120149B2
公开(公告)日：2012-02-21
申请号：US11307128
申请日：2006-01-24
IPC分类号： H01L23/495 , H01L21/82
CPC分类号： H01L23/4951 , H01L23/49548 , H01L24/81 , H01L2224/16 , H01L2224/16237 , H01L2224/16245 , H01L2224/81136 , H01L2224/8114 , H01L2224/81385 , H01L2224/81801 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： An integrated circuit package system is provided forming a lead finger from a padless lead frame, forming a lead tip hole in the lead finger, mounting an integrated circuit die having a solder bump on the lead finger, and reflowing the solder bump on the lead tip hole of the lead finger.
摘要翻译： 提供一种集成电路封装系统，从无铅引线框架形成引线指，在引线指中形成引线尖端孔，将具有焊料凸点的集成电路芯片安装在引线指状物上，并将引线尖端上的焊料凸点回流 导针的孔。
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公开(公告)号：US20110284842A1
公开(公告)日：2011-11-24
申请号：US13196279
申请日：2011-08-02
IPC分类号： H01L23/58
CPC分类号： H01L23/3128 , H01L22/32 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L2224/05553 , H01L2224/05554 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48225 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/06565 , H01L2924/00014 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/32145 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.
摘要翻译： 一种具有层压基座的集成电路封装系统，包括：基座封装，包括：叠层基板条，叠层基板条上的集成电路，集成电路上的模制盖和叠层基板条，以及基板封装 ; 在基础包上裸露的裸片; 所述裸模与所述层叠基板条电连接; 并封装了裸芯片和基底封装。
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公开(公告)号：US07993939B2
公开(公告)日：2011-08-09
申请号：US11459325
申请日：2006-07-21
IPC分类号： H01L21/66
CPC分类号： H01L23/3128 , H01L22/32 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L2224/05553 , H01L2224/05554 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48225 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/06565 , H01L2924/00014 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/32145 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system with laminate base is provided including forming a base package including, forming a laminate substrate strip, mounting an integrated circuit on the laminate substrate strip, forming a molded cover over the integrated circuit and the laminate substrate strip, and performing a strip test of the base package; attaching a bare die to the base package; connecting electrically the bare die to the laminate substrate strip; and encapsulating the bare die and the base package.
摘要翻译： 提供了一种具有层叠基底的集成电路封装系统，包括形成基底封装，包括形成层压衬底条，将集成电路安装在层叠衬底条上，在集成电路和叠层衬底条上形成模制盖， 基础包装的剥离试验; 将裸模附接到基底包装; 将裸模电连接到层压基板条上; 并封装裸芯片和基底封装。
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47.发明申请公开(公告)号：US20100264529A1
公开(公告)日：2010-10-21
申请号：US12823079
申请日：2010-06-24
IPC分类号： H01L23/495 , H01L21/56
CPC分类号： H01L23/49548 , H01L23/49503 , H01L23/552 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4943 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit package system includes: forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle.
摘要翻译： 一种制造集成电路封装系统的方法包括：在所述板和所述外引线之间形成桨，外引线和内引线; 形成所述桨叶的非垂直桨叶边缘和所述内部导杆的面向所述非垂直桨叶边缘的非垂直前缘; 并将集成电路管芯封装在所述桨上。
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48.发明申请INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICE UNITS AND METHOD FOR MANUFACTURING THEREOF 有权具有多个器件单元的集成电路封装系统及其制造方法公开(公告)号：US20100244273A1
公开(公告)日：2010-09-30
申请号：US12797922
申请日：2010-06-10
IPC分类号： H01L23/538 , H01L21/60 , H01L21/56 , H01L23/28
CPC分类号： H01L23/49575 , H01L23/49541 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01027 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A method for manufacturing an integrated circuit package system includes: forming a first device unit, having first external interconnects arranged along a perimeter of the first device unit, and a second device unit, having second external interconnects arranged along a perimeter of the second device unit, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnects; encapsulating with an encapsulation covering the integrated circuit die, the first device unit, and the second device unit with both the first external interconnects and the second external interconnects partially exposed; and forming a partial encapsulation cut in the encapsulation electrically isolating the first external interconnects and the second electrical interconnects.
摘要翻译： 一种用于制造集成电路封装系统的方法，包括：形成具有沿着第一器件单元的周边布置的第一外部互连的第一器件单元和具有沿着第二器件单元的周边布置的第二外部互连的第二器件单元 ，在阵列配置中; 在第一设备单元上安装集成电路管芯; 连接集成电路管芯和第一外部互连件; 封装了覆盖集成电路管芯，第一器件单元和第二器件单元的封装，其中第一外部互连和第二外部互连部分地被部分地暴露; 以及在所述封装中形成电隔离所述第一外部互连和所述第二电互连的部分封装切割。
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公开(公告)号：US20090179314A1
公开(公告)日：2009-07-16
申请号：US12410463
申请日：2009-03-25
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/49579 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2224/1601 , H01L2224/81141 , H01L2224/81192 , H01L2224/81193 , H01L2224/812 , H01L2224/81801 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151
摘要： An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support.
摘要翻译： 一种集成电路封装系统，包括形成具有预定高度的引线支架的引线的引线框架，并且以由引导板支撑件的预定高度确定的预定的折叠高度将集成电路管芯与电互连件连接。
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公开(公告)号：US20090014849A1
公开(公告)日：2009-01-15
申请号：US12237291
申请日：2008-09-24
IPC分类号： H01L23/495 , H01L21/56
CPC分类号： H01L21/568 , H01L23/3135 , H01L23/495 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.
摘要翻译： 提供了一种集成电路封装系统，其从无铅引线框架形成引线，并且封装所述引线以将第一模塑料与第二模塑料一起封装，用于支撑集成电路模具。
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