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    Laminate substrate and semiconductor package utilizing the substrate
    45.
    发明授权
    Laminate substrate and semiconductor package utilizing the substrate 有权
    利用基板的层叠基板和半导体封装

    公开(公告)号：US07919851B2

    公开(公告)日：2011-04-05

    申请号：US12133841

    申请日：2008-06-05

    申请人： Wen-Jeng Fan

    发明人： Wen-Jeng Fan

    IPC分类号： H01L23/12

    CPC分类号： H05K3/3452 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/068 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching.

    摘要翻译： 揭示层叠基板和利用基板的半导体封装。 层叠基板主要包括芯层，第一金属层和设置在芯层的底表面上的第一焊料掩模，以及设置在芯层的顶表面上的第二金属层和第二焊料掩模。 两个焊接掩模具有不同的CTE以补偿由热应力引起的潜在的基板翘曲。 因此，可以减少基板的制造成本，而不增加额外的加强件，也可以改变半导体封装的厚度，以抑制封装工艺期间的基板翘曲。 特别地，芯片安装层通过印刷部分地覆盖第二焊料掩模，并且在预固化之后是平面的，用于零间隙管芯附着。

    SUBSTRATE PANEL
    49.
    发明申请
    SUBSTRATE PANEL 失效
    基板

    公开(公告)号：US20100038118A1

    公开(公告)日：2010-02-18

    申请号：US12191645

    申请日：2008-08-14

    申请人： Wen-Jeng Fan

    发明人： Wen-Jeng Fan

    IPC分类号： H05K1/02

    CPC分类号： H05K3/242 ,  H05K3/0052 ,  H05K2201/09254

    摘要： A substrate panel primarily comprises a plurality of substrate strips arranged in an array, one or more current input lines, a plurality of cascaded lines connecting between the substrate strips, and a current input buffer gate. Current input lines connect a current input side of the substrate panel to the adjacent substrate strips. The current input buffer gate has a frame around the substrate strips and a plurality of meshes where the frame intersects with the current input lines and the meshes intersect with the cascaded lines with both ends of the meshes connecting to the frame. Therefore, the current can be evenly distributed to each substrate strip during plating processes to improve the issues of different plating thicknesses and different plating roughness caused by different current densities and to protect the internal circuits inside the substrate strips from the damages due to current surges and unstable voltages.

    摘要翻译： 衬底面板主要包括布置成阵列的多个衬底条，一个或多个电流输入线，连接在衬底条之间的多条级联线和电流输入缓冲门。 电流输入线将基板面板的电流输入侧连接到相邻的基板条。 当前输入缓冲器门具有围绕衬底条的框架以及框架与当前输入线相交的多个网格，并且网格与连接到框架的网格的两端的级联线相交。 因此，电镀过程中电流可以均匀地分布到每个衬底条上，以改善由不同电流密度引起的不同电镀厚度和不同电镀粗糙度的问题，并保护衬底条内部的电路免受由于电流浪涌引起的损坏， 电压不稳定

    COL (Chip-On-Lead) multi-chip package
    50.
    发明授权
    COL (Chip-On-Lead) multi-chip package 有权
    COL（Chip-On-Lead）芯片封装

    公开(公告)号：US07622794B1

    公开(公告)日：2009-11-24

    申请号：US12133892

    申请日：2008-06-05

    申请人： Wen-Jeng Fan

    发明人： Wen-Jeng Fan

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, the thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.

    摘要翻译： 揭示了芯片引线（COL）多芯片封装，主要包括多个引线，设置在第一引线上的第一芯片，堆叠在第一芯片上的一个或多个第二芯片和密封剂。 引线具有封装在密封剂内部的多个内部引线，其中内部引线完全形成在朝向并平行于密封剂的底表面的凹陷平面上。 位于密封剂顶表面的内部引线之间的高度是内部引线和底部表面之间的高度的三倍或更大。 由于第二芯片的数量和厚度受到控制，所以密封剂的顶表面与最邻近的第二芯片之间的厚度与密封剂的内部引线和底部表面之间的厚度大致相同 。 因此，密封剂中引线没有下弯曲的内部引线可平衡上下模流，并承载更多的芯片而不会移位或倾斜。