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    Hybrid interconnect and system for testing semiconductor dice
    47.
    发明授权
    Hybrid interconnect and system for testing semiconductor dice 失效

    公开(公告)号：US07049840B1

    公开(公告)日：2006-05-23

    申请号：US09302576

    申请日：1999-04-30

    申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  James M. Wark ,  Derek Gochnour

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0466 ,  G01R1/0735

    摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

    Method and apparatus for testing semiconductor dice
    49.
    发明授权
    Method and apparatus for testing semiconductor dice 失效
    测试半导体骰子的方法和装置

    公开(公告)号：US06639416B1

    公开(公告)日：2003-10-28

    申请号：US09897592

    申请日：2001-07-02

    申请人： Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

    发明人： Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

    IPC分类号： G01R3102

    CPC分类号： G01R31/2886 ,  G01R1/0483 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects. In a go second interposer embodiment, the interposer connects to conductors on the base and adapts the base for use with different sized interconnects.

    摘要翻译： 提供了用于测试半导体裸片（例如裸裸片或芯片级封装）的方法和载体。 载体包括用于保持单个管芯的基座，用于建立与管芯的临时电连通的互连件，以及用于偏压管芯并互连在一起的施力机构。 在说明性实施例中，底座包括以适于电连接到不同尺寸的互连件的通用图案布置的导体。 因此，互连在基座上可以互换，用于使用相同的基底测试不同类型的骰子。 基座上的导体可以形成在基座的平面有源表面上或具有不同尺寸的空腔的阶梯式有源表面上，用于安装不同尺寸的互连。在替代实施例中，载体包括插入器。 在第一插入器实施例中，插入器直接连接到外部测试电路，并且可以改变以适应不同尺寸的互连。 在第二插入器实施例中，插入器连接到基座上的导体，并且使基座适配不同大小的互连使用。