公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US20180090391A1

公开(公告)日：2018-03-29

申请号：US15274974

申请日：2016-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mira Park ,  Kwan-Yong Lim ,  Steven Bentley ,  Amitabh Jain

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/223 ,  H01L21/324

CPC classification number: H01L21/823892 ,  H01L21/2236 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

公开(公告)号：US09773708B1

公开(公告)日：2017-09-26

申请号：US15245634

申请日：2016-08-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John Zhang ,  Steven Bentley ,  Kwan-Yong Lim

IPC: H01L21/8238 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.

公开(公告)号：US20170263465A1

公开(公告)日：2017-09-14

申请号：US15598905

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/311 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.

公开(公告)号：US09698025B2

公开(公告)日：2017-07-04

申请号：US14476879

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

公开(公告)号：US09530869B2

公开(公告)日：2016-12-27

申请号：US14643409

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Steven Bentley

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract translation: 本文公开的一种说明性方法包括在器件的源极/漏极区域中形成绝缘材料层，其中绝缘材料层具有与栅极盖层的上表面基本上平面的上表面 使绝缘材料层凹陷，使得其凹陷的上表面暴露在鳍片的表面上，执行另一蚀刻工艺以移除鳍片的至少一部分，从而限定位于凹鳍片上方的凹陷散热片沟槽，并形成外延 所述半导体材料至少部分地位于所述凹陷散热片沟槽中。

公开(公告)号：US09305846B2

公开(公告)日：2016-04-05

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/02 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US20160071930A1

公开(公告)日：2016-03-10

申请号：US14477096

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.

Abstract translation: 一种方法包括在基底上形成第一定向自组装材料。 使用第一定向自组装材料对衬底进行构图，以限定半导体衬底中的至少一个鳍。 第二定向自组装材料形成在至少一个翅片上方以暴露至少一个翅片的顶表面。 在至少一个翅片的顶表面上形成基本垂直的纳米线。 垂直纳米线的至少第一尺寸由第一定向自组装材料的固有间距限定，并且垂直纳米线的第二尺寸由第二定向自组装材料的固有间距限定。

公开(公告)号：US20160071845A1

公开(公告)日：2016-03-10

申请号：US14476879

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在翅片上形成硬掩模层。 第一定向自组装材料形成在硬掩模层之上。 使用第一定向自组装材料的一部分作为蚀刻掩模对硬掩模层进行图案化，以暴露鳍的顶表面的一部分。 在暴露的顶表面上形成基本垂直的纳米线。 基本垂直的纳米线的至少一个维度由第一定向自组装材料的固有间距限定。

公开(公告)号：US09178036B1

公开(公告)日：2015-11-03

申请号：US14492629

申请日：2014-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Naim Moumen ,  Chanro Park ,  Hoon Kim ,  Steven Bentley

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/092 ,  H01L21/28 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one recess etching process such that a first portion of a high-k oxide gate insulation layer and a first portion of a metal oxide layer is positioned entirely within a first gate cavity and a second portion of the high-k oxide gate insulation layer, a conformal patterned masking layer and a second portion of the metal oxide layer is positioned entirely within a second gate cavity, performing at least one heating process to form a composite metal-high-k oxide alloy gate insulation layer in the first gate cavity, while preventing metal from the metal oxide material from being driven into the second portion of the high-k oxide gate insulation layer in the second gate cavity during the at least one heating process, and forming gate electrode structures in the gate cavities.

Abstract translation: 本文公开的一种说明性方法包括进行至少一个凹陷蚀刻工艺，使得高k氧化物栅极绝缘层的第一部分和金属氧化物层的第一部分完全位于第一栅极腔内， 高k氧化物栅极绝缘层的第二部分，共形图案化掩模层和金属氧化物层的第二部分完全位于第二栅极腔内，执行至少一个加热工艺以形成复合金属 - k氧化物合金栅极绝缘层，同时防止来自金属氧化物材料的金属在至少一个加热过程中被驱入第二栅极腔中的高k氧化物栅极绝缘层的第二部分，以及 在门腔中形成栅电极结构。