公开(公告)号：US10121788B1

公开(公告)日：2018-11-06

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US20180261605A1

公开(公告)日：2018-09-13

申请号：US15603827

申请日：2017-05-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

IPC: H01L27/11 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L29/66545 ,  H01L29/66818

Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.

公开(公告)号：US10068987B1

公开(公告)日：2018-09-04

申请号：US15676219

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8234

Abstract: Disclosed are embodiments of a semiconductor structure that includes a vertical field effect transistor (VFET). The VFET has a fin-shaped body that includes a semiconductor fin and an isolation fin. The semiconductor fin extends vertically between lower and upper source/drain regions. The isolation fin is adjacent to and in end-to-end alignment with the semiconductor fin. The VFET gate has a main section that wraps around an outer end and opposing sidewalls of the semiconductor fin and an extension section that extends from the main section along at least the opposing sidewalls of a lower portion the isolation fin and, optionally, around an outer end of that lower portion. A gate contact lands on the isolation fin and extends along the opposing sidewalls and, optionally, the outer end of the isolation fin down to the extension section. Also disclosed are method embodiments for forming these structures.

公开(公告)号：US10014303B2

公开(公告)日：2018-07-03

申请号：US15248889

申请日：2016-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L27/11 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

公开(公告)号：US20180083089A1

公开(公告)日：2018-03-22

申请号：US15271730

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US20180061976A1

公开(公告)日：2018-03-01

申请号：US15797634

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred J. Eller ,  Min-Hwa Chi ,  Jerome J. B. Ciavatti

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/783 ,  H01L27/1104 ,  H01L29/41775 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66795

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

公开(公告)号：US09881738B2

公开(公告)日：2018-01-30

申请号：US14818342

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01G13/00 ,  H01G4/012 ,  H01G4/30 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01G4/012 ,  H01G4/306 ,  H01G4/33 ,  H01L23/5222 ,  H01L28/82 ,  H01L28/90

Abstract: Capacitor structures having first electrodes at least partially embedded within a second electrode, and fabrication methods are presented. The methods include, for instance: providing the first electrodes at least partially within an insulator layer, the first electrodes comprising exposed portions; covering exposed portions of the first electrodes with a dielectric material; and forming the second electrode at least partially around the dielectric covered portions of the first electrodes, the second electrode being physically separated from the first electrodes by the dielectric material. In one embodiment, a method further includes exposing further portions of the first electrodes; and providing a contact structure in electrical contact with the further exposed portions of the first electrodes. In another embodiment, some of the first electrodes are aligned substantially parallel to a first direction and other of the first electrodes are aligned substantially parallel to a second direction, the first and second directions being different directions.

公开(公告)号：US09853117B2

公开(公告)日：2017-12-26

申请号：US15342396

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US09831248B1

公开(公告)日：2017-11-28

申请号：US15425366

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/00 ,  H01L27/108 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/10826 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/10885 ,  H01L27/10891 ,  H01L28/91

Abstract: A semiconductor structure includes an array of fins extending horizontally across a substrate. A plurality of transistors are embedded in the fins. The transistors include a 1st S/D region and a 2nd S/D region defining a channel region therebetween. The transistors have a gate structure disposed over the channel region and extending perpendicular to the fins. An ILD layer is disposed over the structure. The ILD layer includes a plurality of TS trenches disposed over the 1st and 2nd S/D regions. The TS tranches extend parallel to the gate structures. A plurality of storage capacitors are disposed within the TS trenches. The storage capacitors include a 1st metal terminal electrically connected to one of the 1st and 2nd S/D regions, a 2nd metal terminal and a capacitor dielectric disposed therebetween. Each transistor is electrically connected to a single storage capacitor to form an eDRAM cell.

公开(公告)号：US09773781B1

公开(公告)日：2017-09-26

申请号：US15342498

申请日：2016-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jagar Singh ,  Jerome Ciavatti

IPC: H01L29/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A first capacitor plate is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. An insulator layer and a second capacitor plate are disposed on the first capacitor plate forming a MIM capacitor. A pair of capacitor plate contacts are electrically connected to the first capacitor plate and the second capacitor plate.