公开(公告)号：US20230197551A1

公开(公告)日：2023-06-22

申请号：US17558294

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/3178 ,  H01L23/293 ,  H01L21/561 ,  H01L25/0652 ,  H01L25/0655 ,  H01L24/08 ,  H01L2224/08145

Abstract: Techniques and mechanisms for a reconstituted circuit device to be formed using a flow of material, by capillary action, in a region between a first die and a second die. In an embodiment, a rigid mass extends around, and between, the first die and the second die. The rigid mass comprises a first body of a first material, and a second body of second material, wherein the bodies each extend across the region to respective sidewall structures of the first and second dies. In the region, a portion of the first body forms a surface structure which adjoins the second body. A concave or convex shape of the surface structure is an artefact of a meniscus formed by the first material during a liquid state thereof. In another embodiment, the reconstituted circuit device further comprises an interconnect which adjoins, and extends through, the rigid mass.

公开(公告)号：US11676900B2

公开(公告)日：2023-06-13

申请号：US15778398

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Nitin Deshpande ,  Shawna M. Liff ,  Omkar Karhade ,  Amram Eitan ,  Timothy A. Gosselin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/36 ,  H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/13 ,  H01L23/36 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/50 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

公开(公告)号：US11616283B2

公开(公告)日：2023-03-28

申请号：US16122609

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  William J. Lambert ,  Xiaoqian Li ,  Sidharth Dalmia

IPC: H01Q1/22 ,  H03F3/195 ,  H03F3/24 ,  H01Q1/02 ,  H05K1/03

Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.

公开(公告)号：US11552035B2

公开(公告)日：2023-01-10

申请号：US17392598

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498

Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US11127706B2

公开(公告)日：2021-09-21

申请号：US16145999

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC: H01L23/00

Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US11056466B2

公开(公告)日：2021-07-06

申请号：US16552459

申请日：2019-08-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Christopher L. Rumer ,  Nitin Deshpande ,  Robert M. Nickerson

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/54 ,  H01L23/04 ,  H01L25/10 ,  H01L23/498

Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.

公开(公告)号：US20200273775A1

公开(公告)日：2020-08-27

申请号：US16287653

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal

IPC: H01L23/46 ,  H01L23/427 ,  H01L21/48 ,  F28D15/02

Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.

公开(公告)号：US10461003B2

公开(公告)日：2019-10-29

申请号：US15778387

申请日：2016-11-11

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Kedar Dhane

IPC: H01L23/04 ,  H01L23/16 ,  H01L23/00

Abstract: An electronic package that includes a substrate; a die attached to the substrate; an underfill positioned between the die and the substrate due to capillary action; a first support adjacent to the die and attached to the substrate; and a second support mounted on the first support, wherein the second support is closer to the die than the first support, wherein first support surrounds the die and the second support surrounds the die, and wherein the second support is a different material than the first support. The die may be flip chip bonded to the substrate and the underfill may secure the die to the substrate. The first support may be attached to the substrate using an adhesive and the second support may be attached to the first support using an adhesive.

公开(公告)号：US20170323874A1

公开(公告)日：2017-11-09

申请号：US15437237

申请日：2017-02-20

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06593 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/45099

Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.

公开(公告)号：US20250105207A1

公开(公告)日：2025-03-27

申请号：US18473046

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Ashok Deshpande ,  Dimitrios Antartis ,  Gwang-Soo Kim ,  Shawna Marie Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: Systems, apparatus, and articles of manufacture are disclosed to enable integrated circuit packages with double hybrid bonded dies and methods of manufacturing the same include an integrated circuit (IC) package including a first semiconductor die including first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias connected to respective first metal pads of the first semiconductor die, a second semiconductor die including second metal pads of the second semiconductor die, and a hybrid bond layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling ones of the first metal pads to respective ones of the second metal pads, a first one of the third metal vias positioned beyond a lateral side of the first semiconductor die.