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    SPIN TORQUE MRAM FABRICATION USING NEGATIVE TONE LITHOGRAPHY AND ION BEAM ETCHING
    42.
    发明申请
    SPIN TORQUE MRAM FABRICATION USING NEGATIVE TONE LITHOGRAPHY AND ION BEAM ETCHING 有权
    旋转扭矩雕刻和离子束蚀刻的旋转扭矩MRAM制造

    公开(公告)号：US20170062708A1

    公开(公告)日：2017-03-02

    申请号：US14840176

    申请日：2015-08-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  G03F7/70325 ,  G03F7/70425 ,  G11C11/161 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: A method for forming a memory device includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A planarizing layer is etched to establish a pillar of planarizing material defined by the island of photoresist material. A metal layer is etched to form a metal pillar having a diameter about the same as the pillar of planarizing material. A memory stack is etched to form a memory stack pillar having a diameter about the same as the metal pillar. A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

    Abstract translation: 用于形成存储器件的方法包括使用掩模版和具有与光刻胶的极性相反的极性的显影剂掩蔽光致抗蚀剂材料以提供光致抗蚀剂材料岛。 蚀刻平坦化层以建立由光致抗蚀剂材料岛限定的平坦化材料的支柱。 蚀刻金属层以形成直径与平坦化材料的柱大致相同的金属柱。 蚀刻存储器堆叠以形成具有与金属柱大致相同直径的存储堆栈柱。 磁阻存储单元包括具有圆形横截面的磁隧道连接柱。 该柱具有钉扎磁性层，隧道势垒层和自由磁性层。 第一导电触点设置在磁隧道结柱的上方。 第二导电触点设置在磁隧道结柱的下方。

    Sputter and surface modification etch processing for metal patterning in integrated circuits
    46.
    发明授权
    Sputter and surface modification etch processing for metal patterning in integrated circuits 有权
    集成电路中金属图案化的溅射和表面改性蚀刻处理

    公开(公告)号：US09064727B2

    公开(公告)日：2015-06-23

    申请号：US13970678

    申请日：2013-08-20

    Applicant: International Business Machines Corporation

    Inventor： Cyril Cabral, Jr. ,  Benjamin L. Fletcher ,  Nicholas C. M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

    IPC: H01L27/092 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L23/535 ,  H01L21/02109 ,  H01L21/31111 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.

    Abstract translation: 集成电路的一个实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中多条导线中的至少一些具有小于百纳米的间距，以及约八十 和九十度。 集成电路的另一实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中通过提供多层结构中的导电金属层来制造多条导线中的至少一些 制造在晶片上并使用甲醇等离子体溅射蚀刻导电金属层，其中在溅射蚀刻之后保留的导电金属层的一部分形成一个或多个导电线。

    PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS
    48.
    发明申请
    PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS 有权
    在集成电路中绘制过渡金属

    公开(公告)号：US20140159227A1

    公开(公告)日：2014-06-12

    申请号：US13707003

    申请日：2012-12-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Cyril Cabral, JR. ,  Sebastian U. Engelmann ,  Benjamin L. Fletcher ,  Michael S. Gordon ,  Eric A. Joseph

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/48 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

    Abstract translation: 在集成电路中制造导线包括图案化过渡金属层以形成导电线并且在一个或多个导电线中的至少一些导电线上沉积保护盖。 或者，在集成电路中制造导线包括图案化过渡金属层以形成导电线，其中导线具有八十纳米的间距，并且在至少一些导电线上沉积保护盖，其中， 保护帽的厚度介于约5至15纳米之间。 或者，在集成电路中制造导线包括图案化过渡金属层以形成导电线，其中导线具有八十纳米线宽，并且在至少一些导电线上沉积保护盖，其中 保护帽的厚度在大约5至15纳米之间。

    SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
    49.
    发明申请
    SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS 审中-公开
    集成电路中金属图案的溅射和表面改性蚀刻加工

    公开(公告)号：US20140124935A1

    公开(公告)日：2014-05-08

    申请号：US13970204

    申请日：2013-08-19

    Applicant: International Business Machines Corporation

    Inventor： CYRIL CABRAL, JR. ,  Benjamin L. Fletcher ,  Nicholas C.M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

    IPC: H01L23/48 ,  H01L21/3213

    CPC classification number: H01L21/32136 ,  H01L21/32131 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have line widths of less than forty nanometers. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, performing a first sputter etch of the layer of conductive metal using a methanol plasma, and performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines.

    Abstract translation: 集成电路的一个实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中多条导线中的至少一些具有小于40纳米的线宽。 集成电路的另一实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中通过提供多层结构中的导电金属层来制造多条导线中的至少一些 制造在晶片上，使用甲醇等离子体对导电金属层进行第一次溅射蚀刻，以及使用第二等离子体对导电金属层进行第二溅射蚀刻，其中导电金属层的一部分保留在 第二溅射蚀刻形成一个或多个导电线。

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