公开(公告)号：US10249559B2

公开(公告)日：2019-04-02

申请号：US14997846

申请日：2016-01-18

Applicant: International Business Machines Corporation

Inventor： Jae-Woong Nah ,  Charles L. Reynolds ,  Katsuyuki Sakuma

IPC: H01L23/498 ,  H01L21/033 ,  H01L23/00 ,  H01L23/15 ,  H05K7/10 ,  H05K1/00 ,  H05K3/34 ,  H05K3/40

Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.

公开(公告)号：US10130302B2

公开(公告)日：2018-11-20

申请号：US15196558

申请日：2016-06-29

Applicant: International Business Machines Corporation

Inventor： John U. Knickerbocker ,  Shriya Kumar ,  Jae-Woong Nah

IPC: H01L21/768 ,  A61B5/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/532 ,  H01L21/48 ,  H05K1/03 ,  H01L23/00 ,  A61M5/00 ,  B23K3/06 ,  H01L23/538 ,  H01L23/66 ,  H05K3/40 ,  B23K101/36

Abstract: A method includes forming one or more vias in a substrate, forming at least one liner on at least one sidewall of at least one of the vias, and filling said at least one via with solder material using injection molded soldering. The at least one liner may comprise a solder adhesion layer, a barrier layer, or a combination of a barrier layer and a solder adhesion layer.

公开(公告)号：US20180218971A1

公开(公告)日：2018-08-02

申请号：US15936014

申请日：2018-03-26

Applicant: International Business Machines Corporation

Inventor： Eric P. Lewandowski ,  Jae-Woong Nah ,  Peter J. Sorce

IPC: H01L23/498 ,  H01L21/3205 ,  H05K3/12 ,  H05K3/06 ,  H01L21/027 ,  H01L21/48 ,  H01L21/3213

Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.

公开(公告)号：US20180218970A1

公开(公告)日：2018-08-02

申请号：US15935984

申请日：2018-03-26

Applicant: International Business Machines Corporation

Inventor： Eric P. Lewandowski ,  Jae-Woong Nah ,  Peter J. Sorce

IPC: H01L23/498 ,  H01L21/3205 ,  H05K3/12 ,  H05K3/06 ,  H01L21/027 ,  H01L21/48 ,  H01L21/3213

CPC classification number: H01L23/49816 ,  H01L21/0273 ,  H01L21/32051 ,  H01L21/32133 ,  H01L21/4853 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L2224/11 ,  H05K3/064 ,  H05K3/12 ,  H05K3/3457 ,  H05K3/4007 ,  H05K2203/04

Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.

公开(公告)号：US20170199222A1

公开(公告)日：2017-07-13

申请号：US15469501

申请日：2017-03-25

Applicant: International Business Machines Corporation

Inventor： Bing Dang ,  John U. Knickerbocker ,  Jae-Woong Nah ,  Robert E. Trzcinski ,  Cornelia Kang-I Tsang

IPC: G01R1/04 ,  H01L21/66 ,  H01L23/498 ,  G01R1/067

CPC classification number: G01R1/0408 ,  G01R1/06761 ,  G01R3/00 ,  H01L22/30 ,  H01L22/34 ,  H01L23/49838 ,  H01L2224/0401 ,  H01L2224/32145 ,  H01L2224/73265 ,  H01L2924/014

Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

公开(公告)号：US09704822B2

公开(公告)日：2017-07-11

申请号：US14936849

申请日：2015-11-10

Applicant: International Business Machines Corporation

Inventor： John U. Knickerbocker ,  Jae-Woong Nah

IPC: H01L23/00 ,  H01L23/544

CPC classification number: H01L24/81 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/8113 ,  H01L2224/81815 ,  H01L2924/3511

Abstract: Methods are provided for bonding substrates together using alignment structures and solder reflow techniques which achieve self-alignment in three dimensions, as well as semiconductor structures that are formed using such methods. A first alignment structure is formed on a bonding surface of a first substrate, which includes an alignment trench formed in the bonding surface of the first substrate. A second alignment structure is formed on a bonding surface of a second substrate, which includes a bonding pad with solder formed on the bonding pad. The first and second substrates are placed together with the solder of the second alignment structure in contact with the first alignment structure. A solder reflow process causes the solder to melt and flow into the alignment trench while pulling on the bonding pad to cause the second substrate to move into alignment with the first substrate in each of X, Y, and Z directions.

公开(公告)号：US09660116B2

公开(公告)日：2017-05-23

申请号：US15093255

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith E. Fogel ,  Jeehwan Kim ,  Jae-Woong Nah ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L31/0352 ,  H01L31/0236 ,  H01L31/18 ,  H01L31/0224

CPC classification number: H01L31/035227 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/0352 ,  H01L31/1804 ,  Y02E10/50

Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.

公开(公告)号：US09606142B2

公开(公告)日：2017-03-28

申请号：US14495606

申请日：2014-09-24

Applicant: International Business Machines Corporation

Inventor： Bing Dang ,  John U. Knickerbocker ,  Jae-Woong Nah ,  Robert E. Trzcinski ,  Cornelia Kang-I Tsang

IPC: H01L21/8242 ,  G01R1/04

CPC classification number: G01R1/0408 ,  G01R1/06761 ,  G01R3/00 ,  H01L22/30 ,  H01L22/34 ,  H01L23/49838 ,  H01L2224/0401 ,  H01L2224/32145 ,  H01L2224/73265 ,  H01L2924/014

Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

公开(公告)号：US09466590B1

公开(公告)日：2016-10-11

申请号：US14941041

申请日：2015-11-13

Applicant: International Business Machines Corporation

Inventor： Tymon Barwicz ,  Yves C. Martin ,  Jae-Woong Nah

IPC: H01L23/488 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L23/49503 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/30 ,  H01L25/167 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/0225 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06515 ,  H01L2224/09515 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11462 ,  H01L2224/13101 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the major surfaces; a bottom chip stack element comprising a bottom substrate having two major surfaces and bottom solder pads arrayed along a plane of one of the major surfaces; one or more solder reservoir pads connected to one or more of the top solder pads or of the bottom solder pads; and solder material; and wherein at least one of the top solder pads is connected to one of the bottom solder pads by one of the solder material.

Abstract translation: 多芯片系统包括顶部芯片堆叠元件，其包括具有两个主表面的顶部芯片和沿其中一个主表面的平面排列的顶部焊盘; 底部芯片堆叠元件，包括具有两个主表面的底部衬底和沿着主表面之一的平面排列的底部焊盘; 连接到一个或多个顶部焊盘或底部焊盘的一个或多个焊料储存器焊盘; 和焊料; 并且其中所述顶部焊盘中的至少一个通过所述焊料材料之一连接到所述底部焊盘之一。

公开(公告)号：US20160252688A1

公开(公告)日：2016-09-01

申请号：US14634189

申请日：2015-02-27

Applicant: International Business Machines Corporation

Inventor： Tymon Barwicz ,  Yves C. Martin ,  Jae-Woong Nah

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/13 ,  H01L31/173

CPC classification number: G02B6/4238 ,  G02B6/12004 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/4232 ,  H01L24/00

Abstract: Techniques are provided for flip-chip assembly and packaging of microelectronic, photonics and optoelectronic devices in which three-dimensional alignment of package components is achieved using solder surface tension during a solder reflow process to move one or more package components and align such components in X, Y and Z directions using mechanical stops and chip butting techniques.

Abstract translation: 提供了用于微电子，光子学和光电子器件的倒装芯片组装和封装的技术，其中在焊料回流过程期间使用焊料表面张力实现封装部件的三维对准，以移动一个或多个封装部件并将这些部件对准在X ，Y和Z方向使用机械停止和芯片对接技术。