公开(公告)号：US20140327510A1

公开(公告)日：2014-11-06

申请号：US13887788

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Daeik D. Kim ,  David F. Berdy ,  Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Yun ,  Robert P. Mikulka ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H05K9/00 ,  H05K3/10 ,  H05K3/00 ,  H01F5/00 ,  H05K1/11

CPC classification number: H05K9/002 ,  H01F17/0006 ,  H01F27/362 ,  H01F2017/002 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/107

Abstract: An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross-sectional shape than the second via.

Abstract translation: 一种电子设备包括一种结构。 该结构包括第一组直通玻璃通孔（TGV）和第二组TGV。 第一组TGV包括第一通孔，第二组TGV包括第二通孔。 第一通孔具有与第二通孔不同的横截面形状。

公开(公告)号：US20140268616A1

公开(公告)日：2014-09-18

申请号：US13833632

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Changhan Yun ,  David F. Berdy ,  Daeik D. Kim ,  Robert P. Mikulka ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/40 ,  G06F17/5068 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L27/016 ,  H01L27/12 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

Abstract translation: 在特定实施例中，器件包括衬底，至少部分延伸穿过衬底的通孔和电容器。 电容器的电介质位于电容器的通孔和板之间，并且电容器的板在衬底外部和器件内部。

公开(公告)号：US20140167273A1

公开(公告)日：2014-06-19

申请号：US13719984

申请日：2012-12-19

Applicant: QUALCOMM INCORPORATED

Inventor： Jonghae Kim ,  Chengjie Zuo ,  Changhan Yun ,  Mario Francisco Velez ,  Ravindra V. Shenoy ,  Matthew M. Nowak ,  Francesco Carobolante ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Young K. Song

IPC: H01L23/482 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/1517 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10015 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer.

Abstract translation: 一个特征涉及集成电路封装的多层封装衬底，其包括具有至少一个电极的分立电路部件（DCC）。 DCC嵌入在绝缘体层内，并且通孔耦合部件电耦合到电极。 通孔耦合部件的第一部分延伸超过电极的第一边缘，并且多个通孔各自具有耦合到第一通路耦合部件的第一端。 多个通孔中的至少第一通孔耦合到延伸超出电极的第一边缘的通孔连接部件的第一部分。 此外，多个通孔各自具有电耦合到第一外部金属层的第二端，并且通孔连接部件的至少第二部分位于第一内部金属层内。

公开(公告)号：US10553671B2

公开(公告)日：2020-02-04

申请号：US15178900

申请日：2016-06-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez

IPC: H01L29/00 ,  H01L49/02 ,  H01L21/48 ,  H01F17/00 ,  H01L23/522 ,  H01L23/498 ,  H01L23/48 ,  H01L23/64 ,  H01F27/28 ,  H01L23/00

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

公开(公告)号：US10523253B2

公开(公告)日：2019-12-31

申请号：US16029432

申请日：2018-07-06

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu ,  Jonghae Kim ,  David Berdy

IPC: H04B1/16 ,  H01L21/48 ,  H01L23/522 ,  H01L23/64 ,  H01L23/00 ,  H04B1/00 ,  H05K1/16 ,  H05K1/18 ,  H05K3/46 ,  H01L23/498 ,  H01L23/66 ,  H01L27/01 ,  H01L49/02 ,  H01F17/00

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

公开(公告)号：US10319694B2

公开(公告)日：2019-06-11

申请号：US15233902

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik Kim ,  Jie Fu ,  Manuel Aldrete ,  Jonghae Kim ,  Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Mario Francisco Velez

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.

公开(公告)号：US10256863B2

公开(公告)日：2019-04-09

申请号：US15151285

申请日：2016-05-10

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun Gu ,  Chengjie Zuo ,  Steve Fanelli ,  Thomas Gee ,  Young Kyu Song

IPC: H04B1/48 ,  H01L21/84 ,  H01L23/48 ,  H01L23/60 ,  H01L23/66 ,  H01L27/12 ,  H01L29/06 ,  H01L49/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

公开(公告)号：US10154591B2

公开(公告)日：2018-12-11

申请号：US15896959

申请日：2018-02-14

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K5/00 ,  H05K1/18 ,  H03H7/01 ,  H05K3/10 ,  H05K3/30 ,  H05K3/40 ,  H05K1/02 ,  H05K1/14 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28 ,  H01L23/538 ,  H01L23/552

Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.

公开(公告)号：US10141353B2

公开(公告)日：2018-11-27

申请号：US15161152

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Daeik Daniel Kim ,  Jonghae Kim ,  Mario Francisco Velez ,  Chengjie Zuo ,  David Francis Berdy

IPC: H01L27/13 ,  H03H7/01 ,  H01L21/84 ,  H01L49/02 ,  H01L23/498 ,  H03H1/00

Abstract: The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.

公开(公告)号：US10103703B2

公开(公告)日：2018-10-16

申请号：US15161138

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Jonghae Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H03H7/01 ,  H01F5/00 ,  H01F41/04 ,  H01P1/203 ,  H03H7/09 ,  H05K1/18 ,  H03H1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/18 ,  H05K3/40 ,  H01P1/213 ,  H01P5/12 ,  H03H7/46

Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.