中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

84 records (took 0.024 seconds)

    MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING
    41.
    发明申请
    MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING 有权
    基于错误代码跟踪的记忆修复方法和设备

    公开(公告)号：US20170052845A1

    公开(公告)日：2017-02-23

    申请号：US15250677

    申请日：2016-08-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F11/10 ,  G11C29/52 ,  G06F11/16 ,  G11C7/10 ,  H03M13/15 ,  G11C29/44 ,  G11C29/00

    CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  G11C29/765 ,  G11C2029/4402 ,  H03M13/1575

    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

    Abstract translation: 公开了一种存储器模块，其包括衬底，输出读取数据的存储器件和缓冲器。 缓冲器具有用于将读取的数据传送到存储器控制器的主界面和耦合到存储器设备的辅助接口以接收读取的数据。 缓冲器包括用于识别所接收的读取数据中的错误并识别与该错误相关联的存储器件中的存储单元位置的错误逻辑。 修复逻辑将替换存储元素映射为与错误相关联的存储单元位置的替代存储元素。

    Memory with refresh logic to accommodate low-retention storage rows
    43.
    发明授权
    Memory with refresh logic to accommodate low-retention storage rows 有权
    具有刷新逻辑的内存，以适应低保留存储行

    公开(公告)号：US09390782B2

    公开(公告)日：2016-07-12

    申请号：US14306174

    申请日：2014-06-16

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ely Tsern

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

    Abstract: An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate.

    Abstract translation: 公开了一种包括与存储器控制器芯片封装的存储器控​​制器芯片和存储器芯片的装置。 每个存储器芯片包括呈现大于或等于第一时间间隔的保持时间的正常保留存储行，并且已经被测试以生成标识低保留存储行的信息，其表现出小于第一时间间隔的保留时间。 刷新逻辑以对应于第一时间间隔的第一刷新速率刷新正常保留存储行，并且以大于第一刷新率的第二刷新率刷新每个低保留存储行。

    Methods and circuits for dynamically scaling DRAM power and performance
    45.
    发明授权
    Methods and circuits for dynamically scaling DRAM power and performance 有权
    动态缩放DRAM功率和性能的方法和电路

    公开(公告)号：US09256376B2

    公开(公告)日：2016-02-09

    申请号：US14452373

    申请日：2014-08-05

    Applicant: Rambus Inc.

    Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

    IPC: G11C7/00 ,  G06F3/06 ,  G11C11/4074 ,  G06F1/26 ,  G11C5/14

    CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

    Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

    Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

    Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
    46.
    发明申请
    Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device 有权
    包括缓冲器件和集成电路存储器件的存储器系统拓扑

    公开(公告)号：US20140223068A1

    公开(公告)日：2014-08-07

    申请号：US14015648

    申请日：2013-08-30

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G06F13/40

    CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

    Abstract translation: 除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。 例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据， 所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。 集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。 由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。 缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

    Memory system with threaded transaction support
    47.
    发明授权
    Memory system with threaded transaction support 有权

    公开(公告)号：US12197731B2

    公开(公告)日：2025-01-14

    申请号：US18492296

    申请日：2023-10-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G06F12/06 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT
    49.
    发明公开
    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT 审中-公开

    公开(公告)号：US20240111423A1

    公开(公告)日：2024-04-04

    申请号：US18492296

    申请日：2023-10-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G06F12/06 ,  G11C5/04 ,  G11C7/10

    CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

Patent Agency Ranking