公开(公告)号：US10762000B2

公开(公告)日：2020-09-01

申请号：US15662072

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Heehyun Nam ,  Youngsik Kim ,  Youngjin Cho ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/121 ,  G06F12/127 ,  G06F13/16 ,  G06F12/0868

Abstract: A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory, the method including assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines, assigning a validity score to each way based on a degree of validity of the cache line stored in each way, assigning an eviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way, and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.

公开(公告)号：US10394648B2

公开(公告)日：2019-08-27

申请号：US15410752

申请日：2017-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-Hyung Song ,  Jangseok Choi

IPC: G06F11/10 ,  G11C11/4093 ,  G11C29/52

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

公开(公告)号：US10347306B2

公开(公告)日：2019-07-09

申请号：US15231629

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Craig Hanson ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G06F1/32 ,  G06F1/26 ,  G11C7/10 ,  G06F1/3234 ,  G11C5/04 ,  G11C7/22 ,  G06F1/3287 ,  G11C5/14 ,  G11C11/4074

Abstract: A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.

公开(公告)号：US10282294B2

公开(公告)日：2019-05-07

申请号：US15587286

申请日：2017-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0864

Abstract: A system and method for mitigating overhead for accessing metadata for a cache in a hybrid memory module are disclosed. The method includes: providing a hybrid memory module including a DRAM cache, a flash memory, and an SRAM for storing a metadata cache; obtaining a host address including a DRAM cache tag and a DRAM cache index; and obtaining a metadata address from the DRAM cache index, wherein the metadata address includes a metadata cache tag and a metadata cache index. The method further includes determining a metadata cache hit based on a presence of a matching metadata cache entry in the metadata cache stored in the SRAM; in a case of a metadata cache hit, obtaining a cached copy of data included in the DRAM cache and skipping access to metadata included in the DRAM cache; and returning the data obtained from the DRAM cache to a host computer. The SRAM may further store a Bloom filter, and a potential DRAM cache hit may be determined based on a result of a Bloom filter test. A cache controller of the hybrid memory module may disable the Bloom filter when a metadata cache hit ratio is higher than a threshold.

公开(公告)号：US20180285253A1

公开(公告)日：2018-10-04

申请号：US15496936

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/02 ,  G11C8/12

CPC classification number: G06F12/0207 ,  G09G2360/128 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408

Abstract: A hybrid memory includes a plurality of tiles including a plurality of rows including a first row having a first type of memory cells and a second row having a second type of memory cells; a pair of bitline select signals including a bitline select signal and a bitline select bar signal that is an inverse of the bitline select signal; a wordline driver that is configured to receive an input data; a sense amplifier that is configured to output an output data; a write bitline coupled to the first row and the second row; a read bitline coupled to the first row and the second row; a wordline coupled to each of the plurality of rows; and a bitline that is coupled to the write bitline and the read bitline based on set values of the pair of bitline select signals.

公开(公告)号：US09983821B2

公开(公告)日：2018-05-29

申请号：US15161136

申请日：2016-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Frederic Sala ,  Chaohong Hu ,  Hongzhong Zheng ,  Dimin Niu ,  Mu-Tien Chang

IPC: G06F3/06 ,  G06F12/1018

CPC classification number: G06F12/1018 ,  G06F3/0619 ,  G06F3/0641 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0802 ,  G11C29/74

Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

公开(公告)号：US20180102152A1

公开(公告)日：2018-04-12

申请号：US15811576

申请日：2017-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

IPC: G11C8/08 ,  G11C8/18 ,  G11C8/06 ,  G11C8/04 ,  G11C13/00

CPC classification number: G11C8/08 ,  G11C7/1018 ,  G11C8/04 ,  G11C8/06 ,  G11C8/12 ,  G11C8/18 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

公开(公告)号：US20180089087A1

公开(公告)日：2018-03-29

申请号：US15349949

申请日：2016-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Dimin Niu ,  Dongyan Jiang ,  Hongzhong Zheng

IPC: G06F12/0862 ,  G06F12/0868

CPC classification number: G06F12/0862 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/313 ,  G06F2212/6022 ,  G06F2212/6026

Abstract: A method of storing data in a memory module including an in-module prefetcher, an in-module prefetch buffer, memory, and a memory controller, the method including sending address information from the in-module prefetcher to the memory controller and to the prefetch buffer, determining prefetch accuracy based on a comparison of the address information sent to the memory controller and the address information sent to the prefetch buffer, determining a prefetch mode based on the prefetch accuracy, and storing the data in the memory based on the prefetch mode.

公开(公告)号：US20180046541A1

公开(公告)日：2018-02-15

申请号：US15286460

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US20180032437A1

公开(公告)日：2018-02-01

申请号：US15272339

申请日：2016-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tyler Stocksdale ,  Mu-Tien Chang ,  Hongzhong Zheng

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/6028 ,  G11C2207/107 ,  G11C2211/5643 ,  Y02D10/13

Abstract: A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.