公开(公告)号：US20230162764A1

公开(公告)日：2023-05-25

申请号：US17902171

申请日：2022-09-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C7/10 ,  G11C7/22 ,  H03K5/135 ,  H03K5/1534

CPC classification number: G11C7/1066 ,  G11C7/222 ,  H03K5/135 ,  H03K5/1534

Abstract: The present description concerns an electronic device including: a first input configured to receive a clock signal, coupled by a first input buffer to a first circuit; and at least an output coupled by an output buffer to the first circuit, the output buffer being synchronized on first edges of the clock signal, wherein the first input buffer includes a data input coupled to the first input and is configured to maintain the value on its output constant whatever the value on its data input during a duration following each first edge of the clock signal.

公开(公告)号：US10796763B2

公开(公告)日：2020-10-06

申请号：US16256525

申请日：2019-01-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C16/32 ,  G11C16/30 ,  G11C16/10

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.

公开(公告)号：US10560089B2

公开(公告)日：2020-02-11

申请号：US16161531

申请日：2018-10-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Borrel ,  Jimmy Fort ,  Francesco La Rosa

IPC: H03L5/02 ,  H03K17/20 ,  H03K17/22

Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.

公开(公告)号：US10403730B2

公开(公告)日：2019-09-03

申请号：US15914846

申请日：2018-03-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  G11C16/04 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20190067309A1

公开(公告)日：2019-02-28

申请号：US16175030

申请日：2018-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11531 ,  H01L29/861 ,  G11C16/04 ,  H01L29/739 ,  H01L29/66 ,  H01L29/788 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L29/16 ,  H01L27/11526 ,  H01L27/11521 ,  H01L27/08 ,  H01L27/11536 ,  H01L27/12 ,  H01L27/06 ,  H01L29/36

Abstract: An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer.

公开(公告)号：US10218336B2

公开(公告)日：2019-02-26

申请号：US15436817

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: H03L7/099 ,  H03L5/00 ,  G05F3/26 ,  H03K3/03 ,  H03K3/011 ,  G11C7/06 ,  H03L1/00

Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.

公开(公告)号：US09941369B2

公开(公告)日：2018-04-10

申请号：US15195784

申请日：2016-06-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  G11C16/04 ,  H01L21/306

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20170345836A1

公开(公告)日：2017-11-30

申请号：US15364603

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11526 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/266 ,  H01L21/265 ,  H01L29/861 ,  G11C16/04

CPC classification number: H01L27/11531 ,  G11C16/045 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28273 ,  H01L27/0629 ,  H01L27/0814 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/1203 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/66356 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/7394 ,  H01L29/788 ,  H01L29/861

Abstract: A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.

公开(公告)号：US20170278577A1

公开(公告)日：2017-09-28

申请号：US15365433

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/34 ,  G11C16/26 ,  H01L29/788 ,  G11C16/08 ,  H01L27/115 ,  H01L29/792 ,  G11C16/04 ,  G11C16/10

CPC classification number: H01L29/7889 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/788 ,  H01L29/792

Abstract: The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.

公开(公告)号：US20170163291A1

公开(公告)日：2017-06-08

申请号：US15140997

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/70 ,  G11C29/72 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  H03M13/2906

Abstract: A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.