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    3D IC bump height metrology APC
    43.
    发明授权
    3D IC bump height metrology APC 有权

    公开(公告)号：US11075097B2

    公开(公告)日：2021-07-27

    申请号：US16735973

    申请日：2020-01-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Nai-Han Cheng ,  Chi-Ming Yang

    IPC: H01L21/67 ,  G01B11/16 ,  G01B11/14 ,  G01B11/24 ,  H01L21/66 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065

    Abstract: The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a warpage measurement module configured to determine one or more substrate warpage parameters of a substrate. The substrate includes a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate. A metrology module is located physically downstream of the warpage measurement module and has an optical element configured to measure one or more dimensions of the substrate. The metrology module is configured to place the optical element at a plurality of different initial positions, which are directly over a plurality of different locations on the substrate, based upon the one or more substrate warpage parameters. A substrate transport system is configured to transfer the substrate from a first position within the warpage measurement module to a non-overlapping second position within the metrology module.

    3D IC bump height metrology APC
    44.
    发明授权
    3D IC bump height metrology APC 有权

    公开(公告)号：US10541164B2

    公开(公告)日：2020-01-21

    申请号：US16234675

    申请日：2018-12-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Nai-Han Cheng ,  Chi-Ming Yang

    IPC: G01B11/14 ,  G01B11/16 ,  G01B11/24 ,  H01L21/67 ,  H01L21/768 ,  H01L25/00 ,  H01L21/66 ,  H01L21/68 ,  H01L23/00 ,  H01L25/065

    Abstract: The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a substrate warpage measurement module configured to determine one or more substrate warpage parameters of a substrate by taking a plurality of separate measurements at a plurality of different positions over a substrate. The substrate has a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate and a conductive bump disposed over the dielectric structure and configured to be coupled to an additional substrate of a multi-dimensional chip. A substrate metrology module has an optical component and is configured to measure one or more dimensions of the conductive bump. A position control element is configured to move the optical component. A feed-forward path is coupled between an output of the substrate warpage measurement module and an input of the position control element.

    In-situ charging neutralization
    49.
    发明授权
    In-situ charging neutralization 有权
    原位充电中和

    公开(公告)号：US09530617B2

    公开(公告)日：2016-12-27

    申请号：US13753627

    申请日：2013-01-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Jung Wu ,  Jyh-Shiou Hsu ,  Chi-Ming Yang

    IPC: H01J37/32 ,  H01L21/66

    CPC classification number: H01J37/32073 ,  H01J37/32935 ,  H01L22/14 ,  H01L22/20

    Abstract: Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided.

    Abstract translation: 一些实施例涉及用于半导体处理的方法。 在该方法中，设置半导体晶片。 探测半导体晶片的表面区域以确定表面区域上是否存在过量电荷。 基于是否存在过量电荷，选择性地引起电晕放电以减少过量电荷。 还提供其他技术。

    BOTTOM-UP PEALD PROCESS
    50.
    发明申请
    BOTTOM-UP PEALD PROCESS 审中-公开
    底层PEALD工艺

    公开(公告)号：US20160013043A1

    公开(公告)日：2016-01-14

    申请号：US14861441

    申请日：2015-09-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Jung Wu ,  Su-Horng Lin ,  Chi-Ming Yang

    IPC: H01L21/02 ,  H01L21/687 ,  H01L21/285

    CPC classification number: H01L21/0228 ,  C23C16/045 ,  C23C16/45542 ,  H01J37/321 ,  H01J37/3211 ,  H01J37/32357 ,  H01J37/32706 ,  H01J37/32926 ,  H01L21/02274 ,  H01L21/28556 ,  H01L21/687

    Abstract: The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece. The first gas is ionized to from a plurality of ionized precursor molecules. A bias voltage is subsequently applied to the workpiece. The bias voltage attracts the ionized precursor molecules to the workpiece, so as to provide anisotropic coverage of the workpiece with the precursor gas. A reactant gas is introduced into the processing chamber. A plasma is subsequently ignited from the reactant gas, causing the reactant gas to react with the ionized precursor molecules that have been deposited onto the substrate to form a deposited layer on the workpiece.

    Abstract translation: 本公开涉及一种用于执行等离子体增强ALD（PEALD）过程的方法和装置，其提供改进的步骤覆盖。 该方法将前体气体引入到包括半导体工件的处理室中。 将第一气体从多个离子化的前体分子离子化。 随后将偏置电压施加到工件。 偏置电压将离子化的前体分子吸引到工件，以便为前体气体提供工件的各向异性覆盖。 将反应气体引入处理室。 等离子体随后从反应气体中点燃，使反应气体与沉积在基底上的离子化前体分子反应，在工件上形成沉积层。

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