公开(公告)号：US20230378012A1

公开(公告)日：2023-11-23

申请号：US17896840

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Min-Chien Hsiao ,  Chun-Chiang Kuo ,  Tsung-Shu Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/3192 ,  H01L21/568 ,  H01L23/3185 ,  H01L25/0655 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/20 ,  H01L25/105 ,  H01L24/19 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80896 ,  H01L2224/211 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1041 ,  H01L2224/19

Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die; a gap-fill dielectric between a first sidewall of the first integrated circuit die and a second sidewall of the second integrated circuit die; a protective cap overlapping the gap-fill dielectric, the first sidewall of the first integrated circuit die, and the second sidewall of the second integrated circuit die; and an isolation layer around the protective cap, the isolation layer disposed on the first integrated circuit die, and the second integrated circuit die.

公开(公告)号：US11810833B2

公开(公告)日：2023-11-07

申请号：US17373250

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Tsung-Yu Chen ,  Tsung-Shu Lin ,  Chen-Hsiang Lao ,  Wen-Hsin Wei ,  Hsien-Pin Hu

IPC: H01L23/48 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/67 ,  H01L23/40

CPC classification number: H01L23/3675 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4878 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/67092 ,  H01L23/3185 ,  H01L23/40 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16225

Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

公开(公告)号：US20230112750A1

公开(公告)日：2023-04-13

申请号：US18064371

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC: H01L23/00 ,  H01L23/488 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

公开(公告)号：US11527502B2

公开(公告)日：2022-12-13

申请号：US17181202

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC: H01L21/76 ,  H01L21/56 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/683 ,  H01L25/10

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

公开(公告)号：US11069642B2

公开(公告)日：2021-07-20

申请号：US16409880

申请日：2019-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Shu Lin ,  Hsuan-Ning Shih

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.

公开(公告)号：US20210193550A1

公开(公告)日：2021-06-24

申请号：US16718211

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Chien-Yuan Huang ,  Chen-Hsiang Lao

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

公开(公告)号：US20210098330A1

公开(公告)日：2021-04-01

申请号：US16805869

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hui Wang ,  Der-Chyang Yeh ,  Shih-Peng Tai ,  Tsung-Shu Lin ,  Yi-Chung Huang

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°

公开(公告)号：US20200273828A1

公开(公告)日：2020-08-27

申请号：US16281092

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yen Chiu ,  Shou-Yi Wang ,  Tsung-Shu Lin

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures. The second pad structure is disposed over and contacts the second vias, wherein a vertical projection of each of first pad structures overlaps with a vertical projection of the second pad structure, and an overall area of the vertical projections of the first pad structures is smaller than an area of the vertical projection of the second pad structure. The conductive terminal is disposed over and connects with the second pad structure.