公开(公告)号：US06682969B1

公开(公告)日：2004-01-27

申请号：US09652863

申请日：2000-08-31

申请人： Cem Basceri ,  Howard E. Rhodes ,  Gurtej Sandhu ,  F. Daniel Gealy ,  Thomas M. Graettinger

发明人： Cem Basceri ,  Howard E. Rhodes ,  Gurtej Sandhu ,  F. Daniel Gealy ,  Thomas M. Graettinger

IPC分类号： H01L2100

CPC分类号： H01L28/65 ,  H01L21/31637 ,  H01L21/31691 ,  H01L23/5222 ,  H01L27/10852 ,  H01L28/56 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer, so as to provide an oxygen-rich interface layer between the first insulating layer and the second conducting layer, and so as to trap a plurality of oxygen atoms within the second conducting layer. The oxygen-rich interface layer and second conducting layer act as oxygen vacancy sinks for absorbing migrating oxygen vacancies that originate from the first insulating layer to thereby reduce the concentration of oxygen vacancies in the first insulating layer and to thereby reduce the buildup of oxygen vacancies at the interface layer. Thus, the first insulating layer provides an increased dielectric constant and an increased resistance to current flowing therethrough so as to increase the capacitance of the CIC sandwich and so as to reduce leakage currents flowing through the CIC sandwich.

摘要翻译： 一种改进的电荷存储装置及其提供方法，电荷存储装置包括导体 - 绝缘体导体（CIC）三明治。 CIC夹层包括沉积在半导体集成电路上的第一导电层。 CIC夹层还包括以齐平方式沉积在第一导电层上的第一绝缘层。 第一绝缘层包括具有多个氧化物和部分填充氧化物的多个氧原子的结构，其中未填充的氧气定义氧空位的浓度。 CIC夹层还包括在强氧化环境中沉积在第一绝缘层上的第二导电层，以便降低第一绝缘层中氧空位的浓度，从而在第一绝缘层之间提供富氧界面层 和第二导电层，以便在第二导电层内捕获多个氧原子。 富氧界面层和第二导电层用作氧空位吸收器，用于吸收源于第一绝缘层的迁移氧空位，从而降低第一绝缘层中氧空位的浓度，从而减少氧空位的累积 接口层。 因此，第一绝缘层提供增加的介电常数和增加的电流流过其中，从而增加CIC夹层的电容，并且减少流过CIC夹层的漏电流。

公开(公告)号：US06291364B1

公开(公告)日：2001-09-18

申请号：US09386941

申请日：1999-08-31

申请人： F. Daniel Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam N. Al-Shareef ,  Randhir Thakur

发明人： F. Daniel Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam N. Al-Shareef ,  Randhir Thakur

IPC分类号： H01L2631

CPC分类号： H01L21/28202 ,  C30B33/005 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/31662 ,  H01L29/518 ,  Y10S438/903

摘要： A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmosphere to 25 atmosphere N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.

摘要翻译： 公开了一种在高压氧化炉内高压氧化阶段防止N2O变得超临界的方法和装置。 该方法和装置利用催化剂在进入高压氧化炉时催化分解N2O。 该催化剂用于5气压至25气氛N2O和600至750℃温度范围的环境中，这是导致N2O超临界的条件。 通过防止N2O变得超临界，可以控制反应，防止温度和压力尖峰。 催化剂可以选自贵金属过渡金属及其氧化物。 该组可以包括钯，铂，铱，铑，镍，银和金。

公开(公告)号：US6082375A

公开(公告)日：2000-07-04

申请号：US83258

申请日：1998-05-21

申请人： F. Daniel Gealy ,  Husam N. Al-Shareef ,  Scott Jeffrey DeBoer

发明人： F. Daniel Gealy ,  Husam N. Al-Shareef ,  Scott Jeffrey DeBoer

IPC分类号： C23C16/44 ,  C25F3/12

CPC分类号： C23C16/4405 ,  Y10S438/905 ,  Y10S438/911

摘要： The invention encompasses methods of processing internal surfaces of a chemical vapor deposition reactor. In one implementation, material is deposited over internal surfaces of a chemical vapor deposition reactor while processing semiconductor substrates therein. The deposited material is treated with atomic oxygen. After the treating, at least some of the deposited material is etched from the reactor internal surfaces. In one embodiment, first etching is conducted of some of the deposited material from the reactor internal surfaces. After the first etching, remaining deposited material is treated with atomic oxygen. After the treating, second etching is conducted of at least some of the remaining deposited material from the reactor internal surfaces. In one embodiment, the deposited material is first treated with atomic oxygen. After the first treating, first etching is conducted of some of the deposited material from the reactor internal surfaces. After the first etching, second treating is conducted of remaining deposited material with atomic oxygen. After the second treating, second etching is conducted of at least some of the remaining deposited material from the reactor internal surfaces.

公开(公告)号：US5910880A

公开(公告)日：1999-06-08

申请号：US916771

申请日：1997-08-20

申请人： Scott Jeffrey DeBoer ,  F. Daniel Gealy ,  Randhir P. S. Thakur

发明人： Scott Jeffrey DeBoer ,  F. Daniel Gealy ,  Randhir P. S. Thakur

IPC分类号： H01G4/10 ,  H01L21/02 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01G4/06 ,  H01G4/20

CPC分类号： H01L28/40 ,  H01G4/10 ,  H01L21/28568 ,  H01L21/3145 ,  H01L21/31604 ,  H01L28/56

摘要： The invention pertains to semiconductor circuit components and capacitors. In another aspect, the invention includes a capacitor having a) a first capacitor plate; b) a first tantalum-comprising layer over the first capacitor plate; c) a second tantalum-comprising layer over the first tantalum-comprising layer, the second tantalum-comprising layer having nitrogen; and d) a second capacitor plate over the second tantalum-comprising layer. In another aspect, the invention includes a component having: a) a first tantalum-comprising layer; and b) a second tantalum-comprising layer over the first tantalum-comprising layer, the second tantalum-comprising layer having nitrogen.

摘要翻译： 本发明涉及半导体电路部件和电容器。 另一方面，本发明包括具有a）第一电容器板的电容器; b）在第一电容器板上的第一钽包层; c）在所述第一含钽层上的第二含钽层，所述第二含钽层具有氮; 以及d）在所述第二含钽层上的第二电容器板。 在另一方面，本发明包括具有以下成分的组分：a）第一含钽层; 以及b）在所述第一含钽层上的第二含钽层，所述第二含钽层具有氮。

公开(公告)号：US20150123066A1

公开(公告)日：2015-05-07

申请号：US14073927

申请日：2013-11-07

申请人： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

发明人： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

摘要： A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

摘要翻译： 公开了具有降低的电极 - 硫族化物界面电阻的相变存储单元和制造相变存储单元的方法：在电极层和硫族化物层之间形成界面层，并在硫族化物之间提供降低的电阻 的相变存储层和电极层。 示例性实施例提供界面层包括碳化钨，碳化钼，硼化钨或硼化钼，或其组合。 在一个示例性实施例中，界面层包括约1nm至约10nm的厚度。

公开(公告)号：US08497566B2

公开(公告)日：2013-07-30

申请号：US13338527

申请日：2011-12-28

申请人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

发明人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  Y10T29/417

摘要： A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.

摘要翻译： 形成电容器的方法包括在衬底上形成包含TiN的导电的第一电容器电极材料。 含TiN材料的TiN被有效地氧化，形成电阻率不大于1欧姆·厘米的电导率TiO x N y，其中x大于0，y为0至1.4。 在导电TiO x N y上形成电容器电介质。 在电容器电介质上形成导电的第二电容器电极材料。 考虑了其他方面和实现方式，包括独立于制造方法的电容器。

公开(公告)号：US20120037902A1

公开(公告)日：2012-02-16

申请号：US13280556

申请日：2011-10-25

申请人： Cancheepuram V. Srividya ,  Noel Rocklein ,  John Vernon ,  Jeff Nelson ,  F. Daniel Gealy ,  David Korn

发明人： Cancheepuram V. Srividya ,  Noel Rocklein ,  John Vernon ,  Jeff Nelson ,  F. Daniel Gealy ,  David Korn

IPC分类号： H01L29/12

CPC分类号： C23C16/405 ,  C23C16/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40

摘要： The invention includes a dielectric mode from ALD-type methods in which two or more different precursors are utilized with one or more reactants to form the dielectric material. In particular aspects, the precursors are aluminum and hafnium and/or zirconium for materials made from a hafnium precursor, the hafnium oxide is predominantly in a tetragonal crystalline phase.

摘要翻译： 本发明包括来自ALD型方法的介电模式，其中使用两种或更多种不同的前体与一种或多种反应物形成电介质材料。 在特定方面，前体是由铪前体制成的材料的铝和铪和/或锆，氧化铪主要是四方晶相。

公开(公告)号：US20110067629A1

公开(公告)日：2011-03-24

申请号：US12957104

申请日：2010-11-30

申请人： M. Noel Rocklein ,  F. Daniel Gealy

发明人： M. Noel Rocklein ,  F. Daniel Gealy

IPC分类号： C23C16/455

CPC分类号： H01L21/28562 ,  C23C16/405 ,  C23C16/44 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L28/91

摘要： Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step coverage over features such as trenches in trench plate capacitors. Also shown are methods and devices to provide uniform batch reactor layer thicknesses. Also shown are methods for forming alloy layers with high control over composition. Also shown are methods to selectively control growth rate to provide growth only on selected surfaces.

摘要翻译： 示出了用于控制半导体结构中的膜的生长速率的方法和装置。 化学气相沉积方法和装置包括使用选择性地改变沿着表面的沉积速率的反应抑制剂。 一种具体方法包括原子层沉积。 所示的一种方法提供了诸如沟槽板电容器中的沟槽的特征的高阶覆盖。 还示出了提供均匀间歇反应堆层厚度的方法和装置。 还示出了用于形成具有高组成控制的合金层的方法。 还示出了选择性地控制生长速率以仅在所选表面上提供生长的方法。

公开(公告)号：US07635623B2

公开(公告)日：2009-12-22

申请号：US11488587

申请日：2006-07-17

申请人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

发明人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  Y10T29/417

摘要： A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.

摘要翻译： 形成电容器的方法包括在衬底上形成包含TiN的导电的第一电容器电极材料。 含TiN的材料的TiN被有效地氧化以形成电阻率不大于1欧姆·厘米的电导率TiO x N y，其中x大于0且y为0至1.4。 在导电TiO x N y上形成电容器电介质。 在电容器电介质上形成导电的第二电容器电极材料。 考虑了其他方面和实现方式，包括独立于制造方法的电容器。

公开(公告)号：US20090197386A1

公开(公告)日：2009-08-06

申请号：US12419014

申请日：2009-04-06

申请人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

发明人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

IPC分类号： H01L21/8242 ,  H01L21/283 ,  H01L21/768

CPC分类号： H01L21/76879 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S977/773

摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。 在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。 纳米晶须从第一导电表面生长，并被提供为导电的。 提供关于纳米晶须的电绝缘材料。 导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。 考虑了其他方面和实现。