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公开(公告)号：US07646984B1
公开(公告)日：2010-01-12
申请号：US11728915
申请日：2007-03-26
IPC分类号： H04B10/12
CPC分类号： G06F1/105
摘要： Embodiments of an integrated circuit are described. This integrated circuit includes: a clock-generator circuit configured to provide a clock signal; an optical clock path coupled to the clock-generator circuit; and a latch coupled to the optical clock path. This optical clock path is configured to distribute an optical signal corresponding to the clock signal. Furthermore, the optical clock path is configured to optically set a skew value for the optical signal, and is configured to selectively gate distribution of the optical signal to the latch based on activity of the latch. Note that the selective gating is performed optically.
摘要翻译： 描述集成电路的实施例。 该集成电路包括：时钟发生器电路，被配置为提供时钟信号; 耦合到时钟发生器电路的光时钟通路; 以及耦合到光时钟路径的锁存器。 该光时钟路径被配置为分配对应于时钟信号的光信号。 此外，光时钟路径被配置为光学地设置光信号的偏斜值，并且被配置为基于锁存器的活动来选择性地将光信号分配到锁存器。 注意，选择性门控是光学执行的。
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42.发明申请METHOD AND APPARATUS FOR FACILITATING PROXIMITY COMMUNICATION AND POWER DELIVERY 有权促进接近通信和电力交付的方法和装置公开(公告)号：US20090280601A1
公开(公告)日：2009-11-12
申请号：US12502156
申请日：2009-07-13
IPC分类号： H01L21/50
CPC分类号： H01L23/48 , G02B6/12007 , G02B6/29341 , G02B6/43 , H01L24/10 , H01L24/13 , H01L24/72 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L2224/05556 , H01L2224/05572 , H01L2224/05573 , H01L2224/056 , H01L2224/10135 , H01L2224/10165 , H01L2224/13 , H01L2224/13099 , H01L2224/1319 , H01L2224/2919 , H01L2224/81138 , H01L2224/81141 , H01L2224/81801 , H01L2224/83141 , H01L2224/83194 , H01L2224/838 , H01L2224/83851 , H01L2225/06527 , H01L2924/01006 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/10157 , H01L2924/14 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.
摘要翻译： 所描述的实施例提供了一种促进接近通信和功率传递的芯片间对准的系统。 该系统包括第一集成电路芯片和第二集成电路芯片，它们的两个表面具有被配置为彼此对准的相应蚀刻凹坑。 成形结构放置在第一集成电路芯片的蚀刻凹坑中，使得当第二集成电路芯片的相应蚀刻凹坑与第一集成电路芯片的蚀刻凹坑基本对准时，成形结构与 第一集成电路芯片的蚀刻凹坑以及第二集成电路芯片的相应蚀刻凹坑两者，从而使第一集成电路芯片与第二集成电路芯片对准。 在一些实施例中，蚀刻坑井包括用于通过导电成形结构路由功率的导电结构。
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公开(公告)号：US20090179334A1
公开(公告)日：2009-07-16
申请号：US12391137
申请日：2009-02-23
IPC分类号： H01L23/482
CPC分类号： H01L23/48 , H01L25/0652 , H01L25/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip.
摘要翻译： 本发明的一个实施例提供一种用于促进半导体芯片之间的邻近通信的系统。 该系统包括一个基片和一个桥芯片，每个芯片包括有源电路和信号焊盘所在的有源面以及与有源面相对的背面。 桥芯片的主动面接合到基片的有源面。 然后，通过蚀刻使桥接芯片的有源面的识别部分变薄，并且通过平坦化桥芯片的背面去除，从而在桥芯片中形成露出基片的有源面的一部分的开口 。
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公开(公告)号：US07356213B1
公开(公告)日：2008-04-08
申请号：US11728843
申请日：2007-03-26
IPC分类号： G02B6/12
CPC分类号： H01L23/48 , H01L25/0652 , H01L25/0657 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control information associated with the data to the switching elements via an optical control path. These switching elements are configured to selectively couple the input ports to the output ports based on the flow-control information. Furthermore, a given switching element in the switching elements is coupled to a given input port and a given output port via electrical signal paths that are configured to use proximity communication to communicate the data.
摘要翻译： 描述开关的实施例。 该开关包括被配置为接收被配置为输出信号的信号（其包括数据）和输出端口的输入端口。 此外，开关包括开关元件和流量控制机构，其被配置为经由光学控制路径向开关元件提供与数据相关联的流量控制信息。 这些开关元件被配置为基于流量控制信息选择性地将输入端口耦合到输出端口。 此外，开关元件中的给定开关元件通过经配置以使用接近通信来传送数据的电信号路径耦合到给定输入端口和给定输出端口。
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公开(公告)号：US08796811B2
公开(公告)日：2014-08-05
申请号：US13205745
申请日：2011-08-09
IPC分类号： H01L27/12 , H01L21/50 , G02B6/10 , H01L27/146 , H01L27/148
CPC分类号： H01L27/1465 , H01L21/187 , H01L27/14661 , H01L27/1467 , H01L27/14881 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00
摘要： In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device.
摘要翻译： 在混合集成模块中，将半导体管芯面对面地机械耦合到已经去除衬底的集成器件。 例如，集成电路可以包括制造在绝缘体上硅（SOI）晶片上的光学器件，其中背面硅处理器已经被完全去除，从而有助于改进器件性能和高效率地调谐工作波长 光学装置。 此外，半导体管芯可以是提供电力并用作机械处理器和/或电驱动器的VLSI芯片。 相对于具有完整衬底的光学器件，无基底光学器件的热调谐效率可以提高超过100倍，并且相对于其中衬底仅在光学器件附近被去除的光学器件可以提高5倍。
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公开(公告)号：US20130015578A1
公开(公告)日：2013-01-17
申请号：US13182220
申请日：2011-07-13
IPC分类号： H01L23/498 , H01L21/50 , H01L23/48
CPC分类号： H01L25/0657 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/18 , H01L25/50 , H01L2224/13005 , H01L2224/13017 , H01L2224/13027 , H01L2224/13109 , H01L2224/13111 , H01L2224/13147 , H01L2224/14181 , H01L2224/14183 , H01L2224/16105 , H01L2224/16108 , H01L2224/16111 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/481 , H01L2224/48227 , H01L2224/73103 , H01L2224/81138 , H01L2224/81899 , H01L2225/06551 , H01L2225/06555 , H01L2225/06593 , H01L2924/01327 , H01L2924/07802 , H01L2924/12042 , H01L2924/01082 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/00
摘要： In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.
摘要翻译： 在芯片封装中，半导体管芯或芯片（被称为板堆叠）的垂直堆叠中的半导体管芯通过机械耦合到相邻半导体管芯的表面下方的负特性的正特性对准。 此外，芯片封装包括与板堆叠大致成直角的插入板，其沿着板堆的边缘电耦合到半导体管芯。 特别地，靠近插入板的表面（沿着板堆叠的堆叠方向）的电焊盘通过中间导电材料（例如焊料球）电耦合到靠近半导体管芯的边缘的焊盘， 弹簧连接器。 注意，芯片封装可以促进半导体管芯和插入板之间的信号的高带宽通信。
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公开(公告)号：US20120326322A1
公开(公告)日：2012-12-27
申请号：US13165599
申请日：2011-06-21
CPC分类号： H01L24/13 , H01L23/48 , H01L24/16 , H01L24/81 , H01L2224/10126 , H01L2224/131 , H01L2224/1319 , H01L2224/1357 , H01L2224/13609 , H01L2224/13611 , H01L2224/13655 , H01L2224/13671 , H01L2224/16105 , H01L2224/16145 , H01L2224/81097 , H01L2224/81141 , H01L2224/81193 , H01L2224/81194 , H01L2224/81815 , H01L2224/81855 , Y10T428/24479 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2924/01079 , H01L2924/01029 , H01L2924/01028 , H01L2924/01082 , H01L2924/0105
摘要： A chip package includes a substrate having a positive feature, which is defined on a surface of the substrate and which protrudes above a region on the surface proximate to the positive feature. Furthermore, the chip package includes a mechanical reinforcement mechanism defined on the substrate proximate to the positive feature that increases a lateral shear strength of the positive feature relative to the substrate. In this way, the chip package may facilitate increased reliability of a multi-chip module (MCM) that includes the chip package.
摘要翻译： 芯片封装包括具有正特征的衬底，其被限定在衬底的表面上并且突出在接近正特征的表面上的区域上方。 此外，芯片封装包括限定在靠近正特征的基板上的机械加强机构，其增加正特征相对于基板的横向剪切强度。 以这种方式，芯片封装可以促进包括芯片封装的多芯片模块（MCM）的增加的可靠性。
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公开(公告)号：US20120220056A1
公开(公告)日：2012-08-30
申请号：US13467671
申请日：2012-05-09
IPC分类号： H01L21/02
CPC分类号： H01L23/13 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/16147 , H01L2224/16237 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/81141 , H01L2224/81191 , H01L2225/0651 , H01L2225/06517 , H01L2225/06593 , H01L2924/00014 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01051 , H01L2924/01056 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.
摘要翻译： 描述了多芯片模块（MCM）。 该MCM包括至少两个基板，其通过在基板的相对表面上的正和负特征可重新机械耦合。 这些正面和负面的特征相互交织在一起。 特别地，正特征可以与给定的一对负特征匹配，其包括每个基底上的负特征。 此外，给定对中的负特征中的至少一个可以包括硬磁材料，并且给定对中的正特征和另一个负特征可以包括软磁材料，其提供到硬磁体的通量回流路径 材料。 以这种方式，硬磁材料可以促进基板的可重新机械耦合。
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公开(公告)号：US20120207479A1
公开(公告)日：2012-08-16
申请号：US13156144
申请日：2011-06-08
IPC分类号： H04J14/02
CPC分类号： H04J14/02 , G02F1/0147 , G02F1/025 , G02F2203/15 , H04B10/506 , H04B10/572 , H04J14/0212
摘要： An optical device that includes multiple optical modulators having target operating wavelengths that are distributed over a band of wavelengths and actual operating wavelengths is described. For example, the target operating wavelengths of adjacent optical modulators may be separated by a wavelength increment. Moreover, because of differences between the actual operating wavelengths and the target operating wavelengths of the optical modulators, tuning elements may be used to tune the optical modulators so that the actual operating wavelengths match corresponding carrier wavelengths in a set of optical signals. Furthermore, control logic in the optical device may assign the optical modulators to the corresponding carrier wavelengths based at least on differences between the carrier wavelengths and the actual operating wavelengths, thereby reducing an average tuning energy associated with the tuning elements.
摘要翻译： 描述了一种光学装置，其包括具有分布在波长带和实际工作波长上的目标工作波长的多个光调制器。 例如，相邻光调制器的目标工作波长可以被波长增量分开。 此外，由于实际工作波长与光调制器的目标工作波长之间的差异，调谐元件可用于调谐光调制器，使得实际工作波长匹配一组光信号中的对应载波波长。 此外，光学装置中的控制逻辑可以至少基于载波波长和实际工作波长之间的差异将光调制器分配给相应的载波波长，从而减少与调谐元件相关联的平均调谐能量。
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公开(公告)号：US20120207424A1
公开(公告)日：2012-08-16
申请号：US12816935
申请日：2010-06-16
IPC分类号： G02F1/035
CPC分类号： G02B6/1228 , G02F1/01708 , G02F2001/0157
摘要： An integrated circuit that includes an optical waveguide defined in a semiconductor layer is described. In this integrated circuit, light is coupled between the optical waveguide and an optical modulator, which is disposed on the optical waveguide, using 3-dimensional (3-D) taper structures that are proximate to the ends of the optical modulator. The cross-sectional areas of these 3-D taper structures transition, over a distance, from that of the optical waveguide (distal from the optical modulator) to that of optical modulator (proximate to the ends of the optical modulator). In this way, a spatial extent of an optical mode in the optical waveguide and a spatial extent of the optical mode in the optical modulator may be approximately matched to reduce the optical loss when the light is coupled to or from the optical modulator.
摘要翻译： 描述了包括在半导体层中限定的光波导的集成电路。 在该集成电路中，使用靠近光调制器的端部的3维（3-D）锥形结构将光耦合在光波导和设置在光波导上的光调制器之间。 这些3-D锥形结构的横截面积在一段距离上与光波导（远离光调制器）的横截面面积转换到光调制器（近于光调制器的端部）的截面面积。 以这种方式，光学波导中的光学模式的空间范围和光学调制器中的光学模式的空间范围可以近似匹配，以减少当光耦合到光学调制器时的光学损耗。
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