公开(公告)号：US08305054B2

公开(公告)日：2012-11-06

申请号：US12686587

申请日：2010-01-13

申请人： Ke-Horng Chen ,  Jean-Shin Wu ,  Yu-Nong Tsai ,  Ming-Yan Fan

发明人： Ke-Horng Chen ,  Jean-Shin Wu ,  Yu-Nong Tsai ,  Ming-Yan Fan

IPC分类号： G05F3/16

CPC分类号： H02M3/1584 ,  H02M2001/009

摘要： An energy control method for a inductive conversion device comprising: determination of individual error of multiple output voltages; determination of peak current based on the errors, determination of total energy through the peak current and charging to at least one inductor according to the peak current, whereas the inductor will store the total energy.

摘要翻译： 一种用于感应转换装置的能量控制方法，包括：确定多个输出电压的单个误差; 基于误差确定峰值电流，根据峰值电流确定总能量，并根据峰值电流对至少一个电感充电，而电感将存储总能量。

公开(公告)号：US08288273B2

公开(公告)日：2012-10-16

申请号：US13274607

申请日：2011-10-17

申请人： Il Kwan Lee

发明人： Il Kwan Lee

IPC分类号： H01L21/4763

CPC分类号： H01L29/7811 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/7813 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/49111 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/00

摘要： A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

摘要翻译： 公开了用于在半导体芯片晶片顶上形成图案化的厚金属化的方法。 该方法包括制备准备金属化的几乎完整的半导体芯片晶片; 使用热金属工艺沉积次厚度TK1的底部金属层及其内置对准标记; 使用冷金属工艺沉积亚层厚度TK2的顶金属层，从而形成总厚度TK = TK1 + TK2的层叠厚金属化; 然后，使用内置的对准标记作为参考，图案化堆叠的厚金属化。 因此，与冷金属工艺相比，由于与金属工艺相比，热金属工艺具有优异的阶梯覆盖性，因此形成了图案化的金属化，具有更好的金属台阶覆盖的优点; 并且由于与金属热处理相比，冷金属工艺的对准信号噪声特性较低，因此对准误差率降低。

公开(公告)号：US08264084B2

公开(公告)日：2012-09-11

申请号：US11932845

申请日：2007-10-31

申请人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

发明人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

IPC分类号： H01L21/60 ,  H01L23/488

CPC分类号： H01L24/40 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/64 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05624 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

摘要翻译： 提出了一种焊顶增强型半导体器件进行封装。 焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。 至少一个接触区域电连接到至少一个接触增强区域。 每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。 在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。 用于制造焊料顶部器件的方法包括：a）将顶部金属层的光刻图案化成接触区域和接触增强区域。 b）使用用于增加复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

公开(公告)号：US08242013B2

公开(公告)日：2012-08-14

申请号：US12749696

申请日：2010-03-30

申请人： Tao Feng ,  Yueh-Se Ho

发明人： Tao Feng ,  Yueh-Se Ho

IPC分类号： H01L21/4763

CPC分类号： H01L21/561 ,  H01L23/142 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/92 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.

摘要翻译： 公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。 载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘 。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。 厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

公开(公告)号：US08217503B2

公开(公告)日：2012-07-10

申请号：US12881372

申请日：2010-09-14

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

摘要： A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

摘要翻译： 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。

公开(公告)号：US20110103148A1

公开(公告)日：2011-05-05

申请号：US12589945

申请日：2009-10-30

申请人： Anup Bhalla ,  Tinggang Zhu

发明人： Anup Bhalla ,  Tinggang Zhu

IPC分类号： G11C16/04 ,  H01L31/00 ,  H01L21/337

CPC分类号： H01L29/7787 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/785

摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

摘要翻译： 异质结场效应晶体管（HFET）氮化镓（GaN）半导体功率器件包括异质结结构，其包括与两个不同带隙的第二半导体层接口的第一半导体层，从而产生作为二维电子气的界面层 2DEG）层。 功率器件还包括设置在异质结结构的顶部上的栅电极的两个相对侧上的源电极和漏电极，用于控制2DEG层中的源电极和漏电极之间的电流。 功率器件还包括位于栅电极和异质结结构之间的浮动栅极，其中栅电极与浮栅绝缘，并具有绝缘层，并且其中浮置栅极位于上方并且填充有薄绝缘层 异质结结构，并且其中浮置栅极被充电以连续地向2DEG层施加电压以夹紧在源极和漏极之间的2DEG层中流动的电流，由此HFET半导体功率器件是常闭装置。

公开(公告)号：US20110037120A1

公开(公告)日：2011-02-17

申请号：US12583191

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。 非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。 另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。 源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。 另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

公开(公告)号：US20100321840A1

公开(公告)日：2010-12-23

申请号：US12456555

申请日：2009-06-17

申请人： Madhur Bobde

发明人： Madhur Bobde

IPC分类号： H02H9/04 ,  H01L29/866 ,  H01L21/329

CPC分类号： H01L27/0266 ,  H01L29/732

摘要： A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal. The gate may be shorted to the drain for configuring the BS-MOSFET transistor into a two terminal device with a gate-to-source voltage equal to a drain-to-source voltage. The drain/collector/cathode terminal disposed on top of the trench gate turns on the BS-MOSFET upon application of a threshold voltage of the BS-MOSFET thus triggering the bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of the BS-MOSFET.

摘要翻译： 支持在其上支撑外延层的半导体衬底上的低电压瞬变电压抑制（TVS）器件。 TVS器件还包括底源金属氧化物半导体场效应晶体管（BS-MOSFET），其包括被包围在设置在半导体衬底的顶表面附近的体区中的漏极区域围绕的沟槽栅极，其中漏极区域与 构成结二极管的主体区域和包含在构成双极晶体管的外延层顶部的主体区域中的漏极区域，其中顶部电极设置在用作漏极/集电极端子的半导体的顶表面上，并且底部电极设置在 用作源/发射极的半导体衬底的底表面。 主体区域还包括电连接到主体到源短路连接的表面体接触区域，从而将身体区域连接到用作源极/发射极端子的底部电极。 栅极可能短路到漏极，用于将BS-MOSFET晶体管配置为栅极至源极电压等于漏极 - 源极电压的双端子器件。 设置在沟槽栅极顶部的漏极/集电极/阴极端子在施加BS-MOSFET的阈值电压时导通BS-MOSFET，因此触发双极晶体管用于钳位和抑制基本接近阈值电压的瞬态电压 BS-MOSFET。

公开(公告)号：US07842974B2

公开(公告)日：2010-11-30

申请号：US12388390

申请日：2009-02-18

申请人： TingGang Zhu

发明人： TingGang Zhu

IPC分类号： H01L29/47

CPC分类号： H01L29/872 ,  H01L29/08 ,  H01L29/2003 ,  H01L29/417

摘要： A gallium nitride based semiconductor diode includes a substrate, a GaN layer formed on the substrate, an AlGaN layer formed on the GaN layer where the GaN layer and the AlGaN layer forms a cathode region of the diode, a metal layer formed on the AlGaN layer forming a Schottky junction therewith where the metal layer forms an anode electrode of the diode, and a high barrier region formed in the top surface of the AlGaN layer and positioned under an edge of the metal layer. The high barrier region has a higher bandgap energy than the AlGaN layer or being more resistive than the AlGaN layer.

摘要翻译： 氮化镓基半导体二极管包括基板，形成在基板上的GaN层，形成在GaN层和AlGaN层形成二极管阴极区域的GaN层上的AlGaN层，形成在AlGaN层上的金属层 与金属层形成二极管的阳极电极和形成在AlGaN层的顶表面中并位于金属层的边缘下方的高阻挡区域形成肖特基结。 高阻挡区域具有比AlGaN层更高的带隙能量或比AlGaN层更具阻性的能力。

公开(公告)号：US20100276779A1

公开(公告)日：2010-11-04

申请号：US12433358

申请日：2009-04-30

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/34 ,  H01L21/265 ,  H01L21/76 ,  H01L21/20

CPC分类号： H01L29/861 ,  H01L27/0259 ,  H01L29/10 ,  H01L29/6609

摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

摘要翻译： 垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底被重掺杂;第一导电类型的外延层，形成在衬底上，外延层具有第一厚度;以及基极区 形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。 基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。 在一个实施例中，通过高能量注入形成基极区域。 在另一个实施例中，基底区形成为掩埋层。 选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。