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    Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method
    6.
    发明授权
    Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method 有权

    公开(公告)号：US10468526B2

    公开(公告)日：2019-11-05

    申请号：US15836756

    申请日：2017-12-08

    申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

    发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/08

    摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

    SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD
    9.
    发明申请
    SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD 审中-公开
    自对准插图累积模式场效应晶体管（ACCUFET）结构与方法

    公开(公告)号：US20160099351A1

    公开(公告)日：2016-04-07

    申请号：US14507311

    申请日：2014-10-06

    申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

    发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

    CPC分类号： H01L29/7828 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66666 ,  H01L29/7806

    摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

    摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。 半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。 粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。 阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。 这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极 电压Vgs = 0伏。