公开(公告)号：US12026104B2

公开(公告)日：2024-07-02

申请号：US17438844

申请日：2020-03-19

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Craig E. Hampel

IPC: G06F13/16 ,  G06F7/483

CPC classification number: G06F13/1605 ,  G06F7/483

Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

公开(公告)号：US12026038B2

公开(公告)日：2024-07-02

申请号：US18449118

申请日：2023-08-14

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/00 ,  H04L1/08 ,  H04L1/1809

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/004 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/0072 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

公开(公告)号：US20240215149A1

公开(公告)日：2024-06-27

申请号：US18535775

申请日：2023-12-11

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ralf M. Schmitt ,  Yijong Feng

IPC: H05K1/02 ,  H01B5/02 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC classification number: H05K1/0216 ,  H01B5/02 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/5223 ,  H01L2924/0002

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

公开(公告)号：US20240212743A1

公开(公告)日：2024-06-27

申请号：US18555714

申请日：2022-04-14

Applicant: Rambus, Inc.

Inventor： Christopher Haywood

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/42

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/42

Abstract: Technologies for concurrent interface operations of integrated circuit memory devices are described. An integrated circuit memory device includes an input port, a control port, and an output port. The input port receives interleaved input and a first timing reference. The interleaved input includes one or more commands or write data. The control port receives one or more control signals that specify that the interleaved input is the one or more commands or the write data. The output port transmits read data and a second timing reference. The commands or write data can be received concurrently with transmitting the read data.

公开(公告)号：US12014089B2

公开(公告)日：2024-06-18

申请号：US18121231

申请日：2023-03-14

Applicant: Rambus Inc.

Inventor： Frederick Ware

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0683 ,  G06F12/06 ,  G06F13/1689 ,  G06F13/4086 ,  G06F13/4256 ,  G06F13/1684

Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

公开(公告)号：US12007916B2

公开(公告)日：2024-06-11

申请号：US18295143

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G06F13/1678 ,  G06F2212/7206

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US20240177794A1

公开(公告)日：2024-05-30

申请号：US18367381

申请日：2023-09-12

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C29/52 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C29/52 ,  G11C11/4087 ,  G11C11/4093

Abstract: Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.

公开(公告)号：US20240176497A1

公开(公告)日：2024-05-30

申请号：US18519359

申请日：2023-11-27

Applicant: Rambus Inc.

Inventor： Liji GOPALAKRISHNAN ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40622 ,  G06F13/1636

Abstract: ABSTRACT OF DISCLOSURE A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.

公开(公告)号：US11996167B2

公开(公告)日：2024-05-28

申请号：US17636982

申请日：2020-08-14

Applicant: Cryptography Research, Inc.

Inventor： Scott C. Best ,  Mark Evan Marson ,  Joel Wittenauer

IPC: G11C8/16 ,  G06F7/58 ,  G11C8/12 ,  G11C8/20 ,  G11C13/00

CPC classification number: G11C8/16 ,  G06F7/58 ,  G11C8/12 ,  G11C8/20 ,  G11C13/0035

Abstract: A random number generator selects addresses while a ‘scoreboard’ bank of registers (or bits) tracks which addresses have already been output (e.g., for storing or retrieval of a portion of the data.) When the scoreboard detects an address has already been output, a second address which has not been used yet is output rather than the randomly selected one. The second address may be selected from nearby addresses that have not already been output.

公开(公告)号：US20240168873A1

公开(公告)日：2024-05-23

申请号：US18162824

申请日：2021-08-06

Applicant: Rambus Inc.

Inventor： Andrew M. Fuller ,  Barry William Daly ,  Thomas J. Giovannini ,  Lei Luo ,  Masum Hossain

IPC: G06F12/02 ,  G11C11/408

CPC classification number: G06F12/0223 ,  G11C11/4082

Abstract: Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.