公开(公告)号：US4691436A

公开(公告)日：1987-09-08

申请号：US893934

申请日：1986-08-06

申请人： Tadashi Hirao

发明人： Tadashi Hirao

IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/285 ,  H01L21/302 ,  H01L21/314

CPC分类号： H01L21/2257 ,  H01L21/033 ,  H01L21/28525 ,  Y10S148/01 ,  Y10S148/124

摘要： A method for fabricating bipolar transistors comprises a step of forming a multi-layered film consisting of a polysilicon film (600), a silicon nitride film (202) and a silicon oxide film (104) on an emitter region (7) and on an external base region (54, 56), a step of causing the silicon oxide film (104) to recede inwardly from the polysilicon film (600) and silicon nitride (202) film, a step of patterning the polysilicon film (600) by using the inwardly receded oxide film (104) as a mask while defining the external base region (54, 56), a step of forming an emitter region (7) and an active base region (6) by using the patterned polysilicon as an impurity diffusion source while self-alignedly forming an external base region (54, 56), and a step of self-alignedly forming an insulation film (107, 203) for electrical isolation between base and emitter electrode interconnections (9) on the side wall of the polysilicon film (603) by means of anisotropic etching.

摘要翻译： 一种用于制造双极晶体管的方法包括在发射极区域（7）上形成由多晶硅膜（600），氮化硅膜（202）和氧化硅膜（104）组成的多层膜的步骤， 外部基极区域（54,56），使所述氧化硅膜（104）从所述多晶硅膜（600）和氮化硅（202）膜向内退出的工序;使用所述多晶硅膜（600） 作为掩模的内向后退的氧化物膜（104），同时限定外部基极区（54,56）;通过使用图案化多晶硅作为杂质扩散来形成发射极区（7）和有源基区（6）的步骤 源自身对准地形成外部基极区域（54,56）;以及自对准地形成绝缘膜（107,203）的步骤，用于在所述基底侧壁上的基极和发射极电极互连（9）之间进行电隔离， 多晶硅膜（603）。

公开(公告)号：US4675984A

公开(公告)日：1987-06-30

申请号：US777736

申请日：1985-09-19

申请人： Sheng T. Hsu

发明人： Sheng T. Hsu

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/06 ,  H01L21/318

CPC分类号： H01L21/033 ,  H01L21/308 ,  Y10S148/05

摘要： A method of exposing only the top surface of a narrow mesa is disclosed wherein a protective layer may be very precisely formed on a very narrow mesa for subsequent doping of areas adjacent the mesa without doping the mesa itself. A variation of the invention includes forming an opening directly over the narrow mesa so that a contact may be made at only the top surface of the mesa or the upper portion of the mesa may be doped independent of surfaces adjacent the mesa.

摘要翻译： 公开了仅暴露窄台面的顶表面的方法，其中保护层可以非常精确地形成在非常窄的台面上，用于随后掺杂邻近台面的区域而不掺杂台面本身。 本发明的变型包括在窄台面上直接形成开口，使得可以仅在台面的顶表面处形成接触，或者台面的上部可以独立于邻近台面的表面进行掺杂。

公开(公告)号：US4675982A

公开(公告)日：1987-06-30

申请号：US793509

申请日：1985-10-31

申请人： Wendell P. Noble, Jr. ,  Roy E. Scheuerlein ,  William W. Walker

发明人： Wendell P. Noble, Jr. ,  Roy E. Scheuerlein ,  William W. Walker

IPC分类号： H01L21/76 ,  H01L21/033 ,  H01L21/265 ,  H01L21/762 ,  H01L27/10 ,  H01L27/105 ,  H01L21/302 ,  H01L21/263

CPC分类号： H01L21/033 ,  H01L21/76202 ,  H01L27/105 ,  Y10S148/106 ,  Y10S438/981

摘要： A simple process is provided for making two self-aligned recessed oxide isolation regions of different thicknesses which includes the steps of defining first and second spaced apart regions on the surface of a semiconductor substrate, forming a protective layer over the first region, forming a first insulating layer of a given thickness within the second region while the first region is protected by the protective layer, removing the protective layer from the first region and forming a second insulating layer thinner than that of the first layer within the first region. Field regions may be ion implanted prior to forming the insulating layers.

摘要翻译： 提供了一种用于制造两个不同厚度的自对准凹陷氧化物隔离区的简单工艺，其包括在半导体衬底的表面上限定第一和第二间隔开的区域的步骤，在第一区域上形成保护层，形成第一 在所述第一区域被所述保护层保护的同时，在所述第二区域内具有给定厚度的绝缘层，从所述第一区域去除所述保护层，并形成比所述第一区域内的第一绝缘层薄的第二绝缘层。 在形成绝缘层之前，可以离子注入场区域。

公开(公告)号：US4669177A

公开(公告)日：1987-06-02

申请号：US791968

申请日：1985-10-28

申请人： Sebastiano D'Arrigo ,  Michael C. Smayling

发明人： Sebastiano D'Arrigo ,  Michael C. Smayling

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L21/8249 ,  H01L23/532 ,  H01L27/06 ,  H01L29/735 ,  H01L21/20

CPC分类号： H01L21/033 ,  H01L21/8249 ,  H01L23/53271 ,  H01L29/735 ,  H01L2924/0002 ,  Y10S148/096

摘要： A method of forming a lateral bipolar transistor in a semiconductor substrate of a second conductivity type by an MOS or CMOS process which includes growing a thin insulating layer over the substrate and diffusing a tank region of a first type of conductivity into the semiconductor substrate of a polarity opposite to that of the second conductivity type. A strip of polysilicon is deposited around a region between the emitter area and collector area on a face of the substrate over said oxide. Next an emitter region having the form of a band enclosing an undiffused central region within the polysilicon strip and a collector region located outside of the strip are diffused into the tank. The polysilicon prevents diffusion of implanted impurity into the tank region over which is superimposed the polysilicon. An electrically conducting layer is formed over the emitter and a portion of the polysilicon.By using a strip of polysilicon to limit diffusion of the emitter and collector regions and by forming the emitter contact over both the emitter and polysilicon it is possible to achieve a smaller emitter geometry than is otherwise possible.

摘要翻译： 一种通过MOS或CMOS工艺在第二导电类型的半导体衬底中形成横向双极晶体管的方法，其包括在衬底上生长薄绝缘层并将第一类导电性的区域扩散到半导体衬底中 极性与第二导电类型的极性相反。 围绕在所述氧化物上的衬底的表面上的发射极区域和集电极区域之间的区域周围沉积多晶硅条。 接下来，具有包围多晶硅条带内的未扩散中心区域的带的形式的发射极区域和位于条带外部的收集器区域扩散到槽中。 多晶硅防止注入的杂质扩散到叠加多晶硅的槽区中。 在发射极和多晶硅的一部分上形成导电层。 通过使用多晶硅条来限制发射极和集电极区域的扩散，并且通过在发射极和多晶硅两者上形成发射极接触，可以实现比其它可能的更小的发射极几何形状。

公开(公告)号：US4658496A

公开(公告)日：1987-04-21

申请号：US783161

申请日：1985-10-02

申请人： Willy Beinvogl ,  Gerhard Enders ,  Ernst-Guenter Mohr

发明人： Willy Beinvogl ,  Gerhard Enders ,  Ernst-Guenter Mohr

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L21/308

CPC分类号： H01L29/6659 ,  H01L21/033 ,  H01L21/76895 ,  H01L21/823864 ,  H01L29/0847 ,  Y10S148/082 ,  Y10S148/14 ,  Y10S257/90

摘要： A method for manufacturing VLSI MOS-transistor circuits involving the production of transistors by means of a spacer layer technique and ohmic contacts from the gate interconnect to the diffused regions of the substrate (thus providing buried contacts) both being simultaneously generated. Contact holes are provided at the desired location in the substrate before the deposition of the spacer layer occurs across the surface of the substrate. The spacer layer is simultaneously structured at the side walls of the gates and at the side walls of the interconnects which serve as connections. The contact hole region is doped at the same time as the source/drain areas are provided by ion implantation. The combined manufacture of transistors using spacer technology and buried contacts makes it possible to manufacture MOS logic circuits and memory circuits with voltage stable transistors in high packing density.

摘要翻译： 制造涉及通过间隔层技术制造晶体管的VLSI MOS晶体管电路的方法以及从栅极互连到衬底的扩散区域的欧姆接触（从而提供掩埋触点）两者同时产生。 在衬底的表面发生隔离层的沉积之前，在衬底中的期望位置处提供接触孔。 间隔层同时构造在门的侧壁和作为连接的互连的侧壁处。 在通过离子注入提供源极/漏极区域的同时，接触孔区域被掺杂。 使用间隔技术和掩埋触点的晶体管的组合制造使得可以以高封装密度制造具有稳压晶体管的MOS逻辑电路和存储器电路。

公开(公告)号：US4656730A

公开(公告)日：1987-04-14

申请号：US674274

申请日：1984-11-23

申请人： William T. Lynch ,  Louis C. Parrillo

发明人： William T. Lynch ,  Louis C. Parrillo

IPC分类号： H01L21/76 ,  H01L21/033 ,  H01L21/225 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/38 ,  H01L21/461

CPC分类号： H01L21/76232 ,  H01L21/033 ,  H01L21/2253 ,  H01L21/76202 ,  H01L21/763 ,  H01L21/823892 ,  H01L27/0921 ,  Y10S438/938

摘要： A new method for fabricating CMOS devices, as well as the resulting devices, is disclosed. The method involves incorporating dopants into a semiconductor substrate through a region of the substrate surface, and diffusing the implanted dopants into the substrate to form a tub. Prior to the diffusion step, a trench is formed in, and extending beneath, the surface which partially or completely encircles the region. The trench serves to prevent the formation, or reduce the size, of a relatively low dopant concentration region, which would otherwise lead to undesirable leakage currents in the completed CMOS device, and prevents latchup.

摘要翻译： 公开了一种用于制造CMOS器件的新方法以及所得到的器件。 该方法包括通过衬底表面的区域将掺杂剂掺入到半导体衬底中，以及将注入的掺杂剂扩散到衬底中以形成桶。 在扩散步骤之前，在部分地或完全地环绕该区域的表面上形成沟槽并在其下方延伸。 该沟槽用于防止相对低的掺杂剂浓度区域的形成或减小尺寸，否则这将导致完成的CMOS器件中的不期望的泄漏电流，并且防止闭锁。

公开(公告)号：US4653176A

公开(公告)日：1987-03-31

申请号：US709465

申请日：1985-03-07

申请人： Alfred H. Van Ommen

发明人： Alfred H. Van Ommen

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/033 ,  H01L21/22 ,  H01L21/266 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/822 ,  H01L21/38 ,  H01L21/425

CPC分类号： H01L28/20 ,  H01L21/033 ,  H01L21/321 ,  H01L21/32155 ,  Y10S148/077 ,  Y10S148/083 ,  Y10S148/136

摘要： A method of simultaneously manufacturing semiconductor regions having different doping concentrations, for example, for obtaining semiconductor resistors having differences values. Due to difference in the rate of oxidation, oxide edges of different widths can be formed by oxidation of n-type silicon regions thus obtained. According to the invention, ion implantation or deposition takes place through doping windows for each of which the ratio between the window surface area and the surface area to be doped is different. Subsequently, homogeneous doping concentrations are obtained by diffusion.

摘要翻译： 同时制造具有不同掺杂浓度的半导体区域的方法，例如用于获得具有差值的半导体电阻器。 由于氧化速率的差异，可以通过如此获得的n型硅区域的氧化形成不同宽度的氧化物边缘。 根据本发明，通过掺杂窗口进行离子注入或沉积，其中窗口表面积和待掺杂的表面积之间的比例不同。 随后，通过扩散获得均匀的掺杂浓度。

公开(公告)号：US4636826A

公开(公告)日：1987-01-13

申请号：US802499

申请日：1985-11-27

申请人： Jan W. Slotboom ,  Henricus G. R. Maas ,  Johannes A. Appels ,  Francois M. Klaassen

发明人： Jan W. Slotboom ,  Henricus G. R. Maas ,  Johannes A. Appels ,  Francois M. Klaassen

IPC分类号： H01L29/762 ,  H01L21/033 ,  H01L21/339 ,  H01L27/10 ,  H01L29/76 ,  H01L29/772 ,  H01L29/78 ,  H01L29/04

CPC分类号： H01L29/66954 ,  H01L21/033

摘要： In a semiconductor device, for example a SPS memory having narrow coplanar silicon electrodes, the electrodes are formed by etching grooves or slots having a width in the submicron range into a polycrystalline silicon layer with the slot width being defined by the oxidized edge of a silicon auxiliary layer. The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. The covered electrodes are first interconnected pairwise, whereupon they are separated from each other, and are provided with self-aligned contact windows. Thus, the very narrow electrodes can be contracted without technological problems and memory cells of very small dimensions are provided.

公开(公告)号：US4625388A

公开(公告)日：1986-12-02

申请号：US558923

申请日：1983-12-07

申请人： Edward J. Rice

发明人： Edward J. Rice

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L29/7816 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/41766

摘要： A mesa structure field effect transistor includes a semiconductor body with at least one mesa formed on a major surface and an insulating layer on the mesa and overhanging the mesa. Doped regions in the side walls of the mesa define the channel region and source of the transistor, and the semiconductor body defines and drain region. Preferential etching techniques are employed in forming the mesas and the overhanging insulator. The overhanging insulator is employed as a shadow mask in fabricating the transistor.

摘要翻译： 台面结构场效应晶体管包括半导体本体，其具有形成在主表面上的至少一个台面和台面上的绝缘层并且突出于台面。 台面的侧壁中的掺杂区域限定了晶体管的沟道区域和源极，并且半导体本体限定和漏极区域。 优选蚀刻技术用于形成台面和悬垂绝缘体。 在制造晶体管时，悬垂绝缘体用作荫罩。

公开(公告)号：US4587709A

公开(公告)日：1986-05-13

申请号：US501463

申请日：1983-06-06

申请人： Alan B. Fowler ,  Allan M. Hartstein

发明人： Alan B. Fowler ,  Allan M. Hartstein

IPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L21/76 ,  H01L21/225 ,  H01L21/302

CPC分类号： H01L29/66621 ,  H01L21/033 ,  H01L29/66628 ,  Y10S148/082

摘要： A process for defining small dimensions by forming a vertical step in an etchable material; edge depositing a masking material by angularly evaporating a metal; and etching away all of the first material not covered by the masking material; and device obtained by depositing source, drain, and gate defining material.

摘要翻译： 一种通过在可蚀刻材料中形成垂直台阶来定义小尺寸的方法; 通过角度蒸发金属边缘沉积掩模材料; 并且蚀刻掉未被掩蔽材料覆盖的所有第一材料; 以及通过沉积源极，漏极和栅极限定材料获得的器件。