公开(公告)号：US08395251B2

公开(公告)日：2013-03-12

申请号：US11382983

申请日：2006-05-12

Applicant: Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey D. Punzalan ,  Byung Joon Han ,  Kambhampati Ramakrishna

Inventor： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey D. Punzalan ,  Byung Joon Han ,  Kambhampati Ramakrishna

IPC: H01L23/043

CPC classification number: H01L23/49555 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package to the configured leadframe of the second integrated circuit package.

Abstract translation: 提供集成电路封装到封装堆叠系统，包括提供第一集成电路封装，具有构造的引线框架，提供具有所配置的引线框架的第二集成电路封装，以及通过电连接所配置的引线框，形成集成电路封装对 第一集成电路封装到第二集成电路封装的配置的引线框架。

公开(公告)号：US08389338B2

公开(公告)日：2013-03-05

申请号：US13276372

申请日：2011-10-19

Applicant: Yong Liu ,  Qiuxiao Qian

Inventor： Yong Liu ,  Qiuxiao Qian

IPC: H01L21/00

CPC classification number: H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

Abstract translation: 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

公开(公告)号：US20120322201A1

公开(公告)日：2012-12-20

申请号：US13571262

申请日：2012-08-09

Applicant: Tae Seung CHUNG

Inventor： Tae Seung CHUNG

IPC: H01L21/50

CPC classification number: H01L25/105 ,  H01L23/49805 ,  H01L25/16 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips.

Abstract translation: 提供了一种适用于半导体芯片的半导体封装技术的半导体芯片，其半导体芯片不能直接结合在一起的足够小的引脚。 将印刷电路板（PCB）插入到上半导体芯片的引脚和堆叠的半导体芯片的主体的外部之间的空间中。 印刷电路板在对应于各个引脚的位置处包括多个导电图案。 上，下半导体芯片的各个导体图形和相应的各个引脚结合在一起。 PCB在一侧包括多个凹槽图案，凹槽图案具有与半导体芯片的引脚相同的间距。 PCB布置在下半导体芯片的引脚之间，从而容易地布置有堆叠的半导体芯片。

公开(公告)号：US08212342B2

公开(公告)日：2012-07-03

申请号：US12635695

申请日：2009-12-10

Applicant: Zigmund Ramirez Camacho ,  Dioscoro A. Merilo ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

Inventor： Zigmund Ramirez Camacho ,  Dioscoro A. Merilo ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

IPC: H01L23/495

CPC classification number: H01L24/11 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/16145 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/4899 ,  H01L2224/49 ,  H01L2224/731 ,  H01L2224/732 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2224/81986 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/85951 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/37 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/13 ,  H01L2224/45 ,  H01L2924/00012

Abstract: A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die.

Abstract translation: 一种制造集成电路封装系统的方法包括提供具有连接第一管芯附接焊盘和第一多个端子引线的第一可拆卸背衬元件的第一框架。 第一管芯附接到第一管芯附接垫。 提供基板。 第二个裸片连接到基板上。 第一管芯具有多个管芯互连件连接到第二管芯。 在将第一模具连接到第二模具之后，去除第一可拆卸背衬元件。

公开(公告)号：US08159053B2

公开(公告)日：2012-04-17

申请号：US12892739

申请日：2010-09-28

Applicant: Lawrence Douglas Andrews, Jr. ,  Jeffrey S. Leal ,  Simon J. S. McElrea

Inventor： Lawrence Douglas Andrews, Jr. ,  Jeffrey S. Leal ,  Simon J. S. McElrea

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/24137 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/14 ,  H01L2924/00

Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

Abstract translation: 平坦无引线封装包括至少一个安装在引线框上的管芯，并使用导电聚合物或导电油墨电连接到引线。 此外，组件包括使用导电聚合物或导电油墨电连接到引线的堆叠无引线封装。 此外，封装模块包括安装在支撑件上并且使用导电聚合物或导电油墨电连接到支撑体中的电路的堆叠的无引线封装的组件。

公开(公告)号：US20120074544A1

公开(公告)日：2012-03-29

申请号：US13230128

申请日：2011-09-12

Applicant: Masachika MASUDA ,  Koji TOMITA ,  Tadashi OKAMOTO ,  Yasunori TANAKA ,  Hiroshi OHSAWA ,  Kazuyuki MIYANO ,  Atsushi KURAHASHI ,  Hiromichi SUZUKI

Inventor： Masachika MASUDA ,  Koji TOMITA ,  Tadashi OKAMOTO ,  Yasunori TANAKA ,  Hiroshi OHSAWA ,  Kazuyuki MIYANO ,  Atsushi KURAHASHI ,  Hiromichi SUZUKI

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48639 ,  H01L2224/48664 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/834 ,  H01L2224/85005 ,  H01L2224/85439 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1301 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026

Abstract: A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region.

Abstract translation: 一种半导体器件包括：具有管芯焊盘的引线框架和设置在管芯焊盘周围的多个引线;保持在引线框架的管芯焊盘上的半导体元件和用于将引线框架的引线电连接的接合线和 半导体元件。 引线框架，半导体元件和接合线用密封树脂部分密封。 密封树脂部分包括设置在半导体器件上方和周围的中心区域和设置在中心区域周边的边缘区域。 中部地区的厚度大于边缘地区的厚度。

公开(公告)号：US20120064668A1

公开(公告)日：2012-03-15

申请号：US13300088

申请日：2011-11-18

Applicant: Zigmund Ramirez Camacho ,  Jairus Legaspi Pisigan ,  Henry Descalzo Bathan

Inventor： Zigmund Ramirez Camacho ,  Jairus Legaspi Pisigan ,  Henry Descalzo Bathan

IPC: H01L21/56

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/73207 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Abstract translation: 一种集成电路封装系统的制造方法，包括：形成具有外部突起的基部引线和在其间具有凹部的内部突起; 形成具有细长部分的堆叠引线; 将基座集成电路安装在所述内部突起上或所述细长部分下方; 将堆叠引线安装在基极引线和基极集成电路上; 将堆叠集成电路和堆叠引线与堆叠集成电路连接在基极集成电路上; 并且将基极集成电路和堆叠集成电路的至少一部分封装在基极引线和叠置引线上。

公开(公告)号：US08129827B2

公开(公告)日：2012-03-06

申请号：US11855114

申请日：2007-09-13

Applicant: Zigmund Ramirez Camacho ,  Jeffrey D. Punzalan ,  Jairus Legaspi Pisigan ,  Abelardo Jr Hadap Advincula

Inventor： Zigmund Ramirez Camacho ,  Jeffrey D. Punzalan ,  Jairus Legaspi Pisigan ,  Abelardo Jr Hadap Advincula

IPC: H01L23/02

CPC classification number: H01L23/3135 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the external interconnect in the recess.

Abstract translation: 集成电路封装系统包括：形成外部互连; 连接集成电路管芯和外部互连; 形成具有凹部的封装封装，用所述凹部暴露的外部互连部分覆盖所述集成电路管芯; 并将集成电路器件和外部互连件连接在凹槽中。

公开(公告)号：US08114710B2

公开(公告)日：2012-02-14

申请号：US12358387

申请日：2009-01-23

Applicant: Akira Muto ,  Nobuya Koike ,  Katsuo Arai ,  Atsushi Fujiki

Inventor： Akira Muto ,  Nobuya Koike ,  Katsuo Arai ,  Atsushi Fujiki

IPC: H01L21/00

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/433 ,  H01L23/4334 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/33 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/83 ,  H01L25/115 ,  H01L25/117 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40247 ,  H01L2224/4899 ,  H01L2224/73263 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83139 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83885 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/07025 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/37599

Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip. At the same time, paste-like bonding material and a film member are placed between the source terminal 3 and gate terminal and the semiconductor chip. The paste-like bonding material is cured and turned into bonding material. As the result of use of the film members, variation in the thickness of the bonding material is suppressed.

Abstract translation: 提高树脂密封半导体封装的放射性能，进一步提高其制造成品率。 耦合到半导体芯片的背表面漏电极的漏极端子在封装树脂部分的背面露出。 以下部分和端子的一部分暴露在封装树脂部分的顶表面处：耦合到半导体芯片的源极焊盘电极的源极端子的第一部分和耦合到半导体芯片的栅极焊盘电极的栅极端子 。 源极端子和栅极端子的第二部分的剩余部分在封装树脂部分的背面露出。 当制造该半导体器件时，将接合材料和膜构件放置在漏极端子和半导体芯片之间。 同时，在源极端子3和栅极端子与半导体芯片之间放置糊状结合材料和膜部件。 糊状接合材料固化并变成粘结材料。 作为使用膜构件的结果，抑制了接合材料的厚度的变化。

公开(公告)号：US08080867B2

公开(公告)日：2011-12-20

申请号：US12608587

申请日：2009-10-29

Applicant: Zigmund Ramirez Camacho ,  Jairus Legaspi Pisigan ,  Henry Descalzo Bathan

Inventor： Zigmund Ramirez Camacho ,  Jairus Legaspi Pisigan ,  Henry Descalzo Bathan

IPC: H01L23/02

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/73207 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Abstract translation: 一种集成电路封装系统的制造方法，包括：形成具有外部突起的基部引线和在其间具有凹部的内部突起; 形成具有细长部分的堆叠引线; 将基座集成电路安装在所述内部突起上或所述细长部分下方; 将堆叠引线安装在基极引线和基极集成电路上; 将堆叠集成电路和堆叠引线与堆叠集成电路连接在基极集成电路上; 并且将基极集成电路和堆叠集成电路的至少一部分封装在基极引线和叠置引线上。