公开(公告)号：US20240303158A1

公开(公告)日：2024-09-12

申请号：US18604227

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/20 ,  G06F13/00 ,  G11C7/10 ,  G11C11/22 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/00 ,  H03M13/19 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H03M13/458 ,  G06F3/0659 ,  G06F11/1052 ,  G06F11/201 ,  G06F13/00 ,  G11C7/1006 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/19 ,  H03M13/6561

Abstract: Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

公开(公告)号：US20240303087A1

公开(公告)日：2024-09-12

申请号：US18609981

申请日：2024-03-19

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Giuseppe Ferrari ,  Francesco Falanga ,  Massimo Iaculo

IPC: G06F9/4401 ,  G06F12/0871

CPC classification number: G06F9/4406 ,  G06F12/0871

Abstract: Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.

公开(公告)号：US20240302973A1

公开(公告)日：2024-09-12

申请号：US18584635

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph BUEB

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0644 ,  G06F3/0679

Abstract: A system includes a non-volatile memory configured with a wear-leveling media pool, and a controller. The wear-leveling media pool has an initial endurance limit and is divided into a plurality of virtual partitions. Each virtual partition is assigned a respective endurance threshold. The controller is configured to monitor a first endurance parameter for each virtual partition based on the first endurance parameter for a respective virtual partition satisfying or not satisfying the respective endurance threshold of the respective virtual partition, evaluate a second endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold, and allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions.

公开(公告)号：US12088322B2

公开(公告)日：2024-09-10

申请号：US17894777

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: H03M13/19 ,  H03M13/00 ,  H03M13/15

CPC classification number: H03M13/19 ,  H03M13/159 ,  H03M13/617

Abstract: There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

公开(公告)号：US12087719B2

公开(公告)日：2024-09-10

申请号：US17174827

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/05078 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/1701 ,  H01L2224/80051 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/03616 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/05572 ,  H01L2924/00012

Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

公开(公告)号：US12087632B2

公开(公告)日：2024-09-10

申请号：US17542787

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Corey Staller ,  Anilkumar Chandolu

IPC: H01L21/02 ,  H01L21/8234 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/823412 ,  H01L21/02112 ,  H01L21/02225 ,  H01L21/02282 ,  H01L21/02321 ,  H01L21/02343 ,  H01L21/823437 ,  H10B41/27 ,  H10B43/27

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed.

公开(公告)号：US12087393B2

公开(公告)日：2024-09-10

申请号：US17719486

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Peter Mayer ,  Rethin Raj ,  Nobuyuki Umeda ,  Andreas Schneider ,  Casto Salobrena Garcia

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1057

Abstract: Methods, systems, and devices for multi-driver signaling are described. An apparatus may include a first voltage source configured to supply a positive voltage and a second voltage source configured to supply a negative voltage. The apparatus may also include a first driver configured to couple a transmission line of a bus with the first voltage source and a second driver configured to couple the transmission line of the bus with the second voltage source. The first driver may be configured to transfer current to the transmission line based on a configurable resistance of the first driver. And the second driver configured to transfer current from the transmission line of the bus based on a configurable resistance of the second driver.

公开(公告)号：US12087374B2

公开(公告)日：2024-09-10

申请号：US17884107

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G11C11/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

Abstract: Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a target read window budget (RWB) increase, wherein the target RWB increase corresponds to a maximum RWB increase associated with using a different PV voltage offset for each respective programming level of a memory cell. Embodiments can also include segmenting the plurality of wordlines into one or more wordline groups, wherein each wordline group comprises one or more wordlines. Embodiments can further include determining, for each wordline group, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group. Embodiments can include determining an aggregate RWB increase for the block in view of the target adjustment to the parameter of the memory access operation. Embodiments can further include determining that the aggregate RWB increase for the block satisfies a threshold range associated with the target RWB increase. Embodiments can also include modifying the parameter of the memory access operation according to the target adjustment.

公开(公告)号：US12086468B2

公开(公告)日：2024-09-10

申请号：US18200851

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph H. Steinmetz

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A host command is received designating a first interface standard at a first port for exposing a storage element implemented by a non-volatile memory device and a second interface standard at a second port for exposing a persistent memory region (PMR) implemented as a power protected region of a volatile memory device. The non-volatile memory device and the volatile memory device are associated with a first switch for implementing the first interface standard and a second switch for implementing the second interface standard. The first interface standard supports one or more alternate protocols implemented by the second interface standard. The storage element is exposed by designating the first interface standard at the first port and the PMR by designating the second interface standard at the second port. A segment of the PMR is allocated as a cacheable memory marked as visible through, and shared through, the second interface standard.

公开(公告)号：US12086466B2

公开(公告)日：2024-09-10

申请号：US18116526

申请日：2023-03-02

Applicant: Micron Technology, Inc.

Inventor： Mark A. Helm

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations including programming first data to a set of memory cells of a first wordline using a first number of bits per memory cell. Responsive to receiving second data to program to the set of memory cells of the first wordline, the operations further include determining an error rate associated with a second wordline adjacent to the first wordline. Responsive to determining that the error rate satisfies a threshold criterion, the operations further include selecting a second number of bits per memory cell to program the second data to the first wordline and reprograming, using the second number of bits per memory cell, the first wordline storing the first data by programming second data to the set of memory cells while maintaining the first data.