公开(公告)号：US20090098728A1

公开(公告)日：2009-04-16

申请号：US11870649

申请日：2007-10-11

Applicant: Stephan Grunow ,  Thomas McCarroll Shaw ,  Andrew H. Simon ,  Chih-Chao Yang ,  Tiblor Bolom ,  James Werking

Inventor： Stephan Grunow ,  Thomas McCarroll Shaw ,  Andrew H. Simon ,  Chih-Chao Yang ,  Tiblor Bolom ,  James Werking

IPC: H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76805 ,  H01L21/76865

Abstract: The disclosed method forms a via between metallization layers in a semiconductor structure by patterning an insulator layer overlying a first metallization layer to include a via opening. The method lines the via opening with TaN and Ta liners and then sputter etches the via opening deeper through the TaN and Ta liners into the first metallization layer. After sputter etching, the method then lines the via opening with second TaN and Ta liners. Next, the method deposits a conductor into the via opening, thereby connecting the first and second metallization layers.

Abstract translation: 所公开的方法通过图案化覆盖在第一金属化层上的绝缘体层以包括通孔开口在半导体结构中的金属化层之间形成通孔。 该方法用TaN和Ta衬垫将通孔开口排列，然后通过TaN和Ta衬垫将通孔开口溅射到第一金属化层中。 在溅射蚀刻之后，该方法然后将通孔与第二TaN和Ta衬垫分开。 接下来，该方法将导体沉积到通孔开口中，从而连接第一和第二金属化层。

公开(公告)号：US07517736B2

公开(公告)日：2009-04-14

申请号：US11307642

申请日：2006-02-15

Applicant: Sanjay C. Mehta ,  Daniel C. Edelstein ,  John A. Fitzsimmons ,  Stephan Grunow ,  Henry A. Nye, III ,  David L. Rath

Inventor： Sanjay C. Mehta ,  Daniel C. Edelstein ,  John A. Fitzsimmons ,  Stephan Grunow ,  Henry A. Nye, III ,  David L. Rath

IPC: H01L21/82 ,  H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.

Abstract translation: 提供了使得能够使用较不积极的衬里工艺的能力，同时产生已知具有期望的高应力迁移和电迁移可靠性的结构。 本发明通过化学方法制造通孔“锚”（互锁和相互穿透的通孔）来规避低k（约3.2以下）电介质的溅射损伤问题。 这允许在阻挡/种子金属化步骤中消除或显着减少用于在下面的线中产生通孔穿透（“钻孔，气刨”）的溅射蚀刻工艺。 本发明实现上述，同时保持可靠的铜填充和装置结构。

公开(公告)号：US20090085210A1

公开(公告)日：2009-04-02

申请号：US11863724

申请日：2007-09-28

Applicant: Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

Inventor： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/522 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00

Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Abstract translation: 半导体结构及其形成方法。 该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。 该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。 该结构还包括第一ILD层中的第一沟槽。 第一条沟没有完全填满固体材料。 如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的 跨越第一ILD层的金属线的图案密度。

公开(公告)号：US20090001510A1

公开(公告)日：2009-01-01

申请号：US11771298

申请日：2007-06-29

Applicant: Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L29/00 ,  H01L21/02

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

Abstract translation: 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。

公开(公告)号：US07456099B2

公开(公告)日：2008-11-25

申请号：US11420253

申请日：2006-05-25

Applicant: Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Vidhya Ramachandran ,  Theodorus E. Standaert

Inventor： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Vidhya Ramachandran ,  Theodorus E. Standaert

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.

Abstract translation: 半导体结构包括形成在层间电介质（ILD）层内的多个导电线和形成在ILD层和导电线之上的非平面覆盖层，其中覆盖层相对于导电线在第 导线。

公开(公告)号：US07446036B1

公开(公告)日：2008-11-04

申请号：US11958691

申请日：2007-12-18

Applicant: Tibor Bolom ,  Stephan Grunow ,  David Rath ,  Andrew Herbert Simon

Inventor： Tibor Bolom ,  Stephan Grunow ,  David Rath ,  Andrew Herbert Simon

IPC: H01L21/4763 ,  H01L21/461

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

Abstract translation: 微电子结构和制造微电子结构的方法使用位于第一导体层上并形成的介电层。 孔通过介电层定位。 孔径垂直地穿入第一导体层，并且在电介质层下方的第一导体层内横向延伸，而不到达电介质层，以形成延伸和有翅的孔。 可以使用不存在空隙的电镀方法，将连续的通孔和互连件形成为锚固到延伸和有翼的孔中。

公开(公告)号：US20080012142A1

公开(公告)日：2008-01-17

申请号：US11307642

申请日：2006-02-15

Applicant: Sanjay Mehta ,  Daniel Edelstein ,  John Fitzsimmons ,  Stephan Grunow ,  Henry Nye ,  David Rath

Inventor： Sanjay Mehta ,  Daniel Edelstein ,  John Fitzsimmons ,  Stephan Grunow ,  Henry Nye ,  David Rath

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.

Abstract translation: 提供了使得能够使用较不积极的衬里工艺的能力，同时产生已知具有期望的高应力迁移和电迁移可靠性的结构。 本发明通过化学方法制造通孔“锚”（互锁和相互穿透的通孔）来规避低k（约3.2以下）电介质的溅射损伤问题。 这允许在阻挡/种子金属化步骤中消除或显着减少用于在下面的线中产生通孔穿透（“钻孔，气刨”）的溅射蚀刻工艺。 本发明实现上述，同时保持可靠的铜填充和装置结构。

公开(公告)号：US20070117371A1

公开(公告)日：2007-05-24

申请号：US11286877

申请日：2005-11-23

Applicant: Edward Engbrecht ,  Satyavolu Rao ,  Sameer Ajmera ,  Stephan Grunow

Inventor： Edward Engbrecht ,  Satyavolu Rao ,  Sameer Ajmera ,  Stephan Grunow

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76844

Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

Abstract translation: 装置采用具有孔密封衬垫的镶嵌层，并且包括半导体本体。 包括金属互连的金属互连层形成在半导体本体上。 介电层形成在金属互连层上。 导电沟槽特征和导电通孔特征形成在电介质层中。 孔密封衬垫仅沿着导电通孔特征的侧壁并且沿着导电沟槽特征的侧壁和底表面形成。 孔密封衬垫基本上不存在于导电通孔特征的底表面上。

公开(公告)号：US20050082606A1

公开(公告)日：2005-04-21

申请号：US10689348

申请日：2003-10-20

Applicant: Stephan Grunow ,  Satyavolu Papa Rao ,  Noel Russell

Inventor： Stephan Grunow ,  Satyavolu Papa Rao ,  Noel Russell

IPC: H01L23/52 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/76

CPC classification number: H01L21/76846 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/3146 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76865 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A Low K dielectric layer (20) is formed over a semiconductor (10). Trenches (110, 120) are formed in the dielectric layer (2) and a barrier layer (70) is formed in the trenches. The barrier layer has a thickness of X1 over the upper surface of the dielectric layer and X2 on the sidewalls of the trenches where X1 is greater than X2. A second barrier layer (130) can be formed over the first barrier layer (70) and copper (100) is formed over both barrier layers to fill the trench.

Abstract translation: 在半导体（10）上形成低K电介质层（20）。 沟槽（110,120）形成在电介质层（2）中，并且在沟槽中形成阻挡层（70）。 阻挡层在电介质层的上表面和沟槽的侧壁上具有X 1 <1>的厚度，其中X 1 < 大于X 2 2。 可以在第一阻挡层（70）上形成第二阻挡层（130），并且在两个阻挡层上形成铜（100）以填充沟槽。

公开(公告)号：US20050048776A1

公开(公告)日：2005-03-03

申请号：US10649256

申请日：2003-08-27

Applicant: Satyavolu Papa Rao ,  Stephan Grunow ,  Noel Russell

Inventor： Satyavolu Papa Rao ,  Stephan Grunow ,  Noel Russell

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76862 ,  H01L21/76873

Abstract: A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

Abstract translation: 沟槽（70）形成在电介质层（20）中。 使用物理气相沉积在沟槽中形成第一金属层（80）。 使用化学气相沉积在第一金属层（80）上的沟槽（70）中形成第二金属层（100）。 铜（110）用于通过将铜直接电镀到第二金属（100）上来填充沟槽（70）。