公开(公告)号：US5966541A

公开(公告)日：1999-10-12

申请号：US985052

申请日：1997-12-04

申请人： Anant Agarwal

发明人： Anant Agarwal

IPC分类号： G06F9/45

CPC分类号： G06F8/52

摘要： A type mismatch problem in computer programs is said to occur when there is a mismatch between the form or classification of a value encountered during program execution and that anticipated by the program. A method for repairing or testing for many type mismatch problems in programs works by transforming a binary representation of the program into a new binary in which the problem is fixed or identified. The fix or identification is implemented by converting code that operates on variables that can suffer a mismatch into code that correctly accounts for or tests for the mismatch. Static or dynamic correlation methods, and/or control and data flow graphs are used to track certain values, to determine where to install patches and how to adjust branch, jump and procedure call references after patch installation has shifted the target references.

摘要翻译： 据说计算机程序中的类型不匹配问题发生在程序执行期间遇到的值的形式或分类与程序预期的不一致时。 用于修复或测试程序中许多类型不匹配问题的方法通过将程序的二进制表示形式转换成问题被修复或识别的新二进制文件来实现。 修复或识别通过将对可能遭受不匹配的变量进行操作的代码实现，该代码可以正确地解释或测试不匹配的代码。 静态或动态相关方法和/或控制和数据流图用于跟踪某些值，以确定修补程序安装在何处，以及如何在修补程序安装已转移目标引用之后调整分支，跳转和过程调用引用。

公开(公告)号：US09396946B2

公开(公告)日：2016-07-19

申请号：US13229266

申请日：2011-09-09

申请人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Erik Maki ,  Jason Gurganus ,  Daniel Jenner Lichtenwalner

发明人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Erik Maki ,  Jason Gurganus ,  Daniel Jenner Lichtenwalner

IPC分类号： H01L21/3205 ,  H01L21/04 ,  H01L21/02 ,  H01L29/51 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

摘要： Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

摘要翻译： 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：US09269580B2

公开(公告)日：2016-02-23

申请号：US13229276

申请日：2011-09-09

申请人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

发明人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

IPC分类号： H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L21/04 ,  H01L21/02 ,  H01L29/739 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

摘要： Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

摘要翻译： 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：US08680587B2

公开(公告)日：2014-03-25

申请号：US13229749

申请日：2011-09-11

申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/66

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

摘要翻译： 本公开总体上涉及具有衬底，设置在衬底上的漂移层和设置在漂移层的有源区上的肖特基层的肖特基二极管。 选择用于肖特基金属的金属和用于漂移层的半导体材料以在漂移层和肖特基层之间提供低势垒高度的肖特基结。

公开(公告)号：US08664665B2

公开(公告)日：2014-03-04

申请号：US13229752

申请日：2011-09-11

申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/15

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66143 ,  H01L2224/02166 ,  H01L2924/13055 ,  H01L2924/00

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.

摘要翻译： 本发明一般涉及一种肖特基二极管，其具有衬底，设置在衬底上的漂移层以及设置在衬底的有源区上的肖特基层。 在位于肖特基层正下方的漂移层中提供了结屏障阵列。 结势垒阵列的元件通常是漂移层中的掺杂区域。 为了增加这些掺杂区域的深度，可以在要形成结屏障阵列的元件的漂移层的表面中形成单独的凹槽。 一旦凹陷形成在漂移层中，则凹部周围和底部的区域被掺杂以形成连接屏障阵列的相应元件。

公开(公告)号：US08631205B1

公开(公告)日：2014-01-14

申请号：US13491413

申请日：2012-06-07

申请人： David M. Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

发明人： David M. Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

IPC分类号： G06F12/06

CPC分类号： G06F13/24 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/16 ,  G06F13/4022 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/682 ,  H04L49/109

摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

摘要翻译： 一种装置包括多个处理器核心，每个处理器核心包括计算单元和存储器。 该装置还包括互连网络以在处理器核心之间传送数据。 至少一些存储器被配置为处理器核心外部的存储器的高速缓存，并且至少一些处理器核心被配置为通过互连网络传送消息以访问另一处理器核心的高速缓存。

公开(公告)号：US08552435B2

公开(公告)日：2013-10-08

申请号：US12840583

申请日：2010-07-21

申请人： Qingchun Zhang ,  Anant Agarwal

发明人： Qingchun Zhang ,  Anant Agarwal

IPC分类号： H01L29/15

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/66363 ,  H01L29/744

摘要： Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated.

摘要翻译： 公开了补偿半导体晶片上的不均匀蚀刻的电子器件结构及其制造方法。 在一个实施例中，电子设备包括多个层，包括由期望的半导体材料形成的第一掺杂类型的半导体基底层，也由所需半导体材料形成的基底层上的半导体缓冲层，以及一个或多个 在缓冲层上具有更多的第二掺杂类型的接触层。 蚀刻一个或多个接触层以形成电子器件的第二接触区域。 缓冲层在制造电子器件期间减少对半导体基底层的损伤。 优选地，选择半导体缓冲层的厚度以补偿由于在其上制造电子器件的半导体晶片上的不均匀蚀刻而导致的过蚀刻。

公开(公告)号：US08536582B2

公开(公告)日：2013-09-17

申请号：US12622861

申请日：2009-11-20

申请人： Qingchun Zhang ,  Anant Agarwal ,  Doyle Craig Capell ,  Albert Burk ,  Joseph Sumakeris ,  Michael O'Loughlin

发明人： Qingchun Zhang ,  Anant Agarwal ,  Doyle Craig Capell ,  Albert Burk ,  Joseph Sumakeris ,  Michael O'Loughlin

IPC分类号： H01L31/0312

CPC分类号： C30B29/36 ,  C30B23/02 ,  C30B25/20 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/861 ,  H01L29/872

摘要： A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a direction of less than 8°.

摘要翻译： 基于碳化硅的功率器件包括碳化硅漂移层，其具有形成小于8°的<0001>方向的离轴角的平坦表面。

公开(公告)号：US20120326163A1

公开(公告)日：2012-12-27

申请号：US13229276

申请日：2011-09-09

申请人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

发明人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

IPC分类号： H01L29/161 ,  H01L29/49 ,  H01L21/28

CPC分类号： H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

摘要： Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

摘要翻译： 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：US20120280252A1

公开(公告)日：2012-11-08

申请号：US13102510

申请日：2011-05-06

申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L29/12 ,  H01L29/06 ,  H01L29/772

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.