公开(公告)号：US20160218044A1

公开(公告)日：2016-07-28

申请号：US15093528

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L21/66 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US20160190044A1

公开(公告)日：2016-06-30

申请号：US14827361

申请日：2015-08-17

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

Abstract translation: 各种实施例提供了由载体上的层构成的芯片封装，在该层上的另外的载体材料，其中移除其它载体材料的一个或多个部分以及具有一个或多个接触焊盘的芯片，其中芯片被粘附 通过层到载体。 还提供了由多个芯片组成的晶片级封装，所述芯片通过从所述另外的载体材料释放的所述层的多个部分粘附到所述载体。

公开(公告)号：US20150014845A1

公开(公告)日：2015-01-15

申请号：US13939248

申请日：2013-07-11

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall ,  Michael Goroll ,  Rainer Dudek

IPC: H01L23/498 ,  G06F17/50 ,  H01L23/00

CPC classification number: H01L23/04 ,  G06F17/5068 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49811 ,  H01L24/81 ,  H01L25/10 ,  H01L2224/01 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/83447 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/35121 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.

Abstract translation: 半导体封装包括具有相对的第一和第二主表面以及第一和第二主表面之间的侧面的支撑衬底，附接到支撑衬底的一个主表面的半导体管芯以及至少部分地覆盖支撑衬底的封装材料 和半导体管芯。 突起从支撑基板的一侧向外延伸并终止在封装材料中。 突起形成与封装材料的互锁连接。 互锁连接通过突起增加了封装材料与支撑基板侧面之间的界面的拉伸强度。

公开(公告)号：US20140138843A1

公开(公告)日：2014-05-22

申请号：US13681079

申请日：2012-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L23/538 ,  H01L21/58 ,  H01L21/78

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。

公开(公告)号：US20140138841A1

公开(公告)日：2014-05-22

申请号：US13678675

申请日：2012-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3171 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side.

Abstract translation: 提供一种集成电路，所述集成电路包括：具有第一芯片侧和与所述第一芯片侧相对的第二芯片侧的芯片，所述芯片在所述第二芯片侧具有至少一个接触区域; 封装材料至少部分覆盖芯片; 以及至少一个接触通孔，其包括与所述至少一个接触区域接触并延伸穿过所述封装材料并通过所述芯片在所述第一芯片侧和所述第二芯片侧之间的导电材料。

公开(公告)号：US08652866B2

公开(公告)日：2014-02-18

申请号：US13733375

申请日：2013-01-03

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Georg Meyer-Berg ,  Horst Theuss

IPC: H01L21/56 ,  H01L23/28

CPC classification number: H01L21/563 ,  G01L9/0054 ,  G01L19/0627 ,  G01L19/141 ,  G01L19/147 ,  G01L19/148 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element.

Abstract translation: 传感器装置及方法。 一个实施例提供了具有感测区域的第一半导体芯片。 多孔结构元件附接到第一半导体芯片。 多孔结构元件的第一区域面向第一半导体芯片的感测区域。 封装材料部分地封装第一半导体芯片和多孔结构元件。