公开(公告)号：US11056593B2

公开(公告)日：2021-07-06

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A Young

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/18 ,  H01L21/3105 ,  H01L21/8252

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US10998495B2

公开(公告)日：2021-05-04

申请号：US16329721

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/10 ,  H01L41/187 ,  H01L41/193 ,  H01L41/20 ,  G11C11/16 ,  H01L41/00 ,  H01L27/22 ,  H01L43/08 ,  H01F10/32 ,  H01L43/02 ,  H01F10/12

Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.

公开(公告)号：US10957844B2

公开(公告)日：2021-03-23

申请号：US16346872

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jasmeet S. Chawla ,  Sasikanth Manipatruni ,  Robert L. Bristol ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00 ,  H03K19/18

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

公开(公告)号：US20200372333A1

公开(公告)日：2020-11-26

申请号：US16989371

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Hai Li ,  Ian A. Young

IPC: G06N3/063 ,  H03K3/03

Abstract: Disclosed herein are staged oscillators for neural computing, as well as related methods and assemblies. In some embodiments, neural computing circuitry may include a first oscillator set, a second oscillator set, and an averaging structure coupled between the first oscillator set and the second oscillator set.

公开(公告)号：US20200211608A1

公开(公告)日：2020-07-02

申请号：US16349575

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/14 ,  H03K19/18 ,  H03K19/185

Abstract: An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

公开(公告)号：US20190325932A1

公开(公告)日：2019-10-24

申请号：US16464260

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

Abstract: An apparatus is provided which comprises: a first paramagnet; a stack of layers, a portion of which is adjacent to the first paramagnet, wherein the stack of layers is to provide an inverse Rashba-Edelstein effect; a second paramagnet; a magnetoelectric layer adjacent to the second paramagnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

公开(公告)号：US20190036018A1

公开(公告)日：2019-01-31

申请号：US16081001

申请日：2016-03-29

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Ravi Pillarisetty ,  Uygar E. Avci

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  G11C11/16 ,  G11B5/738

Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.

公开(公告)号：US09729106B2

公开(公告)日：2017-08-08

申请号：US14943209

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  George I. Bourianoff

IPC: H01L43/08 ,  H03B15/00 ,  H01L43/12 ,  H01F10/32 ,  H01F41/30 ,  H03L7/26 ,  B82Y40/00 ,  H01S1/02

CPC classification number: H03B15/006 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/308 ,  H01L43/08 ,  H01L43/12 ,  H01S1/02 ,  H03L7/26

Abstract: A spin torque oscillator and a method of making same. The spin torque oscillator is configured to generate microwave electrical oscillations without the use of a magnetic field external thereto, the spin torque oscillator having one of a plurality of input nanopillars and a nanopillar having a plurality of free FM layers.

公开(公告)号：US09711215B2

公开(公告)日：2017-07-18

申请号：US14913676

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  G11C5/02 ,  G11C5/06 ,  G11C5/08 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C2213/79 ,  G11C2213/82

Abstract: Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.

公开(公告)号：US09570139B2

公开(公告)日：2017-02-14

申请号：US14696965

申请日：2015-04-27

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/00 ,  G11C11/16 ,  H03K19/16

CPC classification number: H01L29/66984 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/16

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

Abstract translation: 描述了一种用于自旋状态元件器件的装置，其包括：可变电阻磁极（VRM）器件，用于接收磁控制信号以调节VRM器件的电阻; 以及耦合到VRM装置的磁逻辑门控（MLG）装置，以接收磁逻辑输入并对磁逻辑输入执行逻辑运算，并且基于VRM装置的电阻来驱动输出磁信号。 描述的磁解除多路复用器包括：第一VRM装置，用于接收磁控制信号以调整第一VRM的电阻; 第二VRM装置，用于接收所述磁控信号以调整所述第二VRM装置的电阻; 以及耦合到第一和第二VRM装置的MLG装置，MLG装置具有至少两个输出磁体，以基于第一和第二VRM装置的电阻输出磁信号。