公开(公告)号：US10783966B2

公开(公告)日：2020-09-22

申请号：US16593530

申请日：2019-10-04

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

IPC: G11C11/16 ,  G11C13/00 ,  G11C7/04 ,  H01L45/00

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

公开(公告)号：US10324793B2

公开(公告)日：2019-06-18

申请号：US15909929

申请日：2018-03-01

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/05 ,  H03M13/27 ,  H03M13/00 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

公开(公告)号：US10073731B2

公开(公告)日：2018-09-11

申请号：US14091757

申请日：2013-11-27

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G06F11/10 ,  H03M13/05 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23 ,  H03M13/29

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.

公开(公告)号：US10026460B2

公开(公告)日：2018-07-17

申请号：US15415690

申请日：2017-01-25

Applicant: Intel Corporation

Inventor： Rakesh Jeyasingh ,  Nevil N. Gajera ,  Mase J. Taub ,  Kiran Pangal

IPC: G11C13/00 ,  G11C7/12 ,  G11C11/56

Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

公开(公告)号：US09852789B2

公开(公告)日：2017-12-26

申请号：US15333096

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Sandeep Guliani ,  Balaji Srinivasan ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/70

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

公开(公告)号：US09824767B1

公开(公告)日：2017-11-21

申请号：US15197124

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Feng Pan ,  Prashant S. Damle ,  Hanmant Pramod Belgal ,  Kiran Pangal

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C16/3427 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2013/0052 ,  G11C2013/0057 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2481 ,  H01L45/06

Abstract: A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.

公开(公告)号：US09792963B2

公开(公告)日：2017-10-17

申请号：US14938221

申请日：2015-11-11

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Frank T. Hady ,  Paul D. Ruby ,  Kiran Pangal ,  Sowmiya Jayachandran

IPC: G11C11/406 ,  G11C7/10 ,  G11C16/34

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3431

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

公开(公告)号：US09652321B2

公开(公告)日：2017-05-16

申请号：US14493956

申请日：2014-09-23

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/02 ,  H03M13/11 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G06F11/10 ,  G06F11/1068 ,  G06F11/108 ,  G06F12/0246 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1108

Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.

公开(公告)号：US09619324B2

公开(公告)日：2017-04-11

申请号：US14126310

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Zion S. Kwok ,  Ravi H. Motwani ,  Kiran Pangal ,  Prashant S. Damle

IPC: G06F11/10 ,  G06F12/00 ,  G11C29/52 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/00 ,  G06F2212/7207 ,  G11C29/52 ,  H03M13/1515 ,  H03M13/152

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US09530523B2

公开(公告)日：2016-12-27

申请号：US14314200

申请日：2014-06-25

Applicant: Intel Corporation

Inventor： Gayathri Rao Subbu ,  Kiran Pangal ,  Nathan Franklin

IPC: G11C29/00 ,  G11C29/52 ,  G11C13/00 ,  G06F11/10 ,  G11C7/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/008 ,  G11C2213/76

Abstract: The present disclosure relates to thermal disturb as heater in cross-point memory. An apparatus includes a memory controller. The memory controller is configured to identify a target memory cell in response to at least one of a selection failure and a set fail memory read error associated with the target memory cell. The memory controller is further configured to apply a first sequence of recovery pulses to a first number of selected adjacent memory cells adjacent the target memory cell, the first sequence of recovery pulses configured to induce heating in the target memory cell.

Abstract translation: 本公开涉及作为交叉点存储器中的加热器的热干扰。 一种装置包括存储器控制器。 存储器控制器被配置为响应于与目标存储器单元相关联的选择故障和设置的故障存储器读取错误中的至少一个来识别目标存储器单元。 存储器控制器还被配置为将第一序列的恢复脉冲施加到与目标存储器单元相邻的第一数量的所选择的相邻存储单元，所述第一恢复脉冲序列被配置为在目标存储单元中感应加热。