公开(公告)号：US09991355B2

公开(公告)日：2018-06-05

申请号：US15068973

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/417 ,  H01L21/285 ,  H01L21/311 ,  H01L21/265 ,  H01L21/02 ,  H01L21/321 ,  H01L23/532 ,  H01L23/535 ,  H01L29/51 ,  H01L29/78 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L29/49 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

公开(公告)号：US20180046597A1

公开(公告)日：2018-02-15

申请号：US15232177

申请日：2016-08-09

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Pierce I-Jen Chuang ,  Li-Wen Hung ,  Jui-Hsin Lai

IPC: G06F15/78 ,  G06N3/063

CPC classification number: G06F15/7892 ,  G06F7/58 ,  G06N3/063 ,  G06N3/082

Abstract: A random number signal generator used for performing dropout or weight initialization for a node in a neural network. The random number signal generator includes a transistor which generates a random noise signal. The transistor includes a substrate, source and drain regions formed in the substrate, a first insulating layer formed over a channel of the transistor, a first trapping layer formed over the first insulating layer, a second insulating layer formed over the first trapping layer, and a second trapping layer formed over the second insulating layer. One or more traps in the first and second trapping layers are configured to capture or release one or more carriers flowing through the channel region. The random noise signal is generated as a function of one or more carrier being captured or released by the one or more traps.

公开(公告)号：US09704867B2

公开(公告)日：2017-07-11

申请号：US15219922

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/04 ,  H01L29/10 ,  H01L21/308 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/306

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

公开(公告)号：US20170047445A1

公开(公告)日：2017-02-16

申请号：US14823344

申请日：2015-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/165 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

Abstract translation: 用于形成杂化互补金属氧化物半导体（CMOS）器件的方法包括将绝缘体上半导体（SOI）衬底的半导体层与SOI的基底衬底取向，通过蚀刻将基底衬底暴露在N阱区中 通过掩模层，电介质层，半导体层和掩埋电介质形成沟槽并在沟槽的侧壁上形成间隔物。 基底衬底从沟槽的底部外延生长以形成延伸区域。 翅片材料从沟槽内的延伸区域外延生长。 掩模层和电介质层在沟槽上恢复。 P型场效应晶体管（PFET）鳍片被蚀刻在基底衬底上，并且在半导体层中蚀刻N型场效应晶体管（NFET）鳍片。

公开(公告)号：US09530864B2

公开(公告)日：2016-12-27

申请号：US14314404

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Michael J. Hargrove ,  Chia-Yu Chen ,  Ryan O. Jung ,  Sivanandha K. Kanakasabapathy ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836

Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地，至少一种方法包括：在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层，所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管，并且使用极其突出的接头实现良好控制的栅极重叠几何，其表面位置使用该组间隔层限定。

公开(公告)号：US09368591B2

公开(公告)日：2016-06-14

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L21/338 ,  H01L29/45

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20150380514A1

公开(公告)日：2015-12-31

申请号：US14314404

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Michael J. Hargrove ,  Chia-Yu Chen ,  Ryan O. Jung ,  Sivanandha K. Kanakasabapathy ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836

Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地，至少一种方法包括：在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层，所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管，并且使用极其突出的接头实现良好控制的栅极重叠几何，其表面位置使用该组间隔层限定。

公开(公告)号：US11604647B2

公开(公告)日：2023-03-14

申请号：US16558536

申请日：2019-09-03

Applicant: International Business Machines Corporation

Inventor： Xiao Sun ,  Chia-Yu Chen ,  Naigang Wang ,  Jungwook Choi ,  Kailash Gopalakrishnan

IPC: G06F17/18 ,  G06N20/00 ,  G06N5/04 ,  G06F9/30 ,  G06F7/483

Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor includes first and second sets of arithmetic units having first and second precision for floating-point computations, the second precision being lower than the first precision. The processor is configured to obtain a machine learning model trained in the first precision, to utilize the second set of arithmetic units to perform inference on input data, to utilize the first set of arithmetic units to generate feedback for updating parameters of the second set of arithmetic units based on the inference performed on the input data by the second set of arithmetic units, to tune parameters of the second set of arithmetic units based at least in part on the feedback generated by the first set of arithmetic units, and to utilize the second set of arithmetic units with the tuned parameters to generate inference results.

公开(公告)号：US10940554B2

公开(公告)日：2021-03-09

申请号：US16205296

申请日：2018-11-30

Applicant: International Business Machines Corporation

Inventor： Li-Wen Hung ,  Jui-Hsin Lai ,  Chia-Yu Chen ,  Ko-Tao Lee

IPC: B23K1/00 ,  A61B5/00 ,  A61B5/1473 ,  A61B5/15 ,  B23K101/36 ,  A61B5/145

Abstract: Methods of fabricating a probe are described. In an example, a structure may be formed on a surface of a substrate. The structure may include the probe, a hinge, and an anchor arranged linearly, where an angle is formed between the probe and the hinge. The hinge may be positioned between the probe and the anchor, and the structure may be parallel to the substrate. An amount of solder may be deposited on an area of the structure that spans from a portion of the probe to a portion of the anchor, and across the hinge. The deposited solder may be reshaped by an execution of a solder reflow process. The reshape of the deposited solder may cause the probe to rotate about the hinge in order to reduce the angle between the probe and the hinge.

公开(公告)号：US20210064985A1

公开(公告)日：2021-03-04

申请号：US16558585

申请日：2019-09-03

Applicant: International Business Machines Corporation

Inventor： Xiao Sun ,  Jungwook Choi ,  Naigang Wang ,  Chia-Yu Chen ,  Kailash Gopalakrishnan

IPC: G06N3/08 ,  G06N3/04

Abstract: An apparatus for training and inferencing a neural network includes circuitry that is configured to generate a first weight having a first format including a first number of bits based at least in part on a second weight having a second format including a second number of bits and a residual having a third format including a third number of bits. The second number of bits and the third number of bits are each less than the first number of bits. The circuitry is further configured to update the second weight based at least in part on the first weight and to update the residual based at least in part on the updated second weight and the first weight. The circuitry is further configured to update the first weight based at least in part on the updated second weight and the updated residual.