公开(公告)号：US10304803B2

公开(公告)日：2019-05-28

申请号：US15147807

申请日：2016-05-05

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Bongsub Lee ,  Belgacem Haba ,  Sangil Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

公开(公告)号：US20190098271A1

公开(公告)日：2019-03-28

申请号：US16206549

申请日：2018-11-30

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H04N9/43 ,  H01L27/146 ,  H04N9/76 ,  H04N5/33 ,  H04N9/04 ,  H04N9/097 ,  G02B27/10 ,  G06T1/20 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/374

Abstract: HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

公开(公告)号：US10217720B2

公开(公告)日：2019-02-26

申请号：US15624494

申请日：2017-06-15

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar

IPC: H01L25/10 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

公开(公告)号：US10177114B2

公开(公告)日：2019-01-08

申请号：US14952482

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Sangil Lee ,  Liang Wang ,  Guilian Gao

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31

Abstract: Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

公开(公告)号：US20180114747A1

公开(公告)日：2018-04-26

申请号：US15334606

申请日：2016-10-26

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Wael Zohni ,  Liang Wang ,  Akash Agrawal

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/562

Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.

公开(公告)号：US09953957B2

公开(公告)日：2018-04-24

申请号：US14639942

申请日：2015-03-05

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Liang Wang

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L25/00 ,  H01L23/36

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/373 ,  H01L24/00 ,  H01L24/11 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/11334 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/2761 ,  H01L2224/32245 ,  H01L2224/81815 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/10253

Abstract: A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

公开(公告)号：US09905523B2

公开(公告)日：2018-02-27

申请号：US15203013

申请日：2016-07-06

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Arkalgud R. Sitaram

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/09 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08168 ,  H01L2224/08501 ,  H01L2224/73204 ,  H01L2224/80487 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1304 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

公开(公告)号：US09812433B2

公开(公告)日：2017-11-07

申请号：US15153188

申请日：2016-05-12

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Liang Wang

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15333 ,  H01L2924/014 ,  H01L2924/00

Abstract: A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies.

公开(公告)号：US20170309518A1

公开(公告)日：2017-10-26

申请号：US15649457

申请日：2017-07-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/82 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US09769923B2

公开(公告)日：2017-09-19

申请号：US15380172

申请日：2016-12-15

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K13/04 ,  H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.