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    Efficient error correction of multi-bit errors
    54.
    发明授权
    Efficient error correction of multi-bit errors 有权
    多位错误的有效纠错

    公开(公告)号：US09362953B2

    公开(公告)日：2016-06-07

    申请号：US13958047

    申请日：2013-08-02

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel ,  Christian Badack

    IPC: H03M13/15 ,  G06F11/08 ,  H03M13/00

    CPC classification number: H03M13/15 ,  G06F11/08 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/6575

    Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·α3ji+Zw2·α2ji+Zw1·αji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)≠(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value Δvi= for the bit position i may then be determined on the basis of the error correction expression evaluated for αji.

    Abstract translation: 用于纠错的电路包括多个子电路，用于确定要用作纠错表达式（z1i，z2i，...，zmi）= Zw3·α3ji+ Zw2·α2ji中的系数的中间值Zw0，Zw1，Zw2，Zw3 + Zw1·αji+ Zw0。 中间值Zw0，Zw1，Zw2，Zw3根据子信号s1，s3，s5确定，以便在1位，2位或3位错误的情况下zi =（z1i，z2i，...， zi =（z1i，z2i，...，zmi）≠（0,0，...，0）当位位置i发生错误时， 当位位置i没有发生错误时。 然后可以基于针对αji评估的误差校正表达式来确定位位置i的校正值＆Dgr; vi =。

    Marker Programming in Non-Volatile Memories
    55.
    发明申请
    Marker Programming in Non-Volatile Memories 有权
    非易失性存储器中的标记编程

    公开(公告)号：US20150347227A1

    公开(公告)日：2015-12-03

    申请号：US14289311

    申请日：2014-05-28

    Applicant: Infineon Technologies AG

    Inventor： Thomas Rabenalt ,  Ulrich Backhausen ,  Thomas Kern ,  Michael Goessel

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1012 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13

    Abstract: A method for accessing a non-volatile memory is presented. The method comprises reading a first memory region of the non-volatile memory and ascertaining whether the first memory region contains a predetermined data pattern. The predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method also comprises evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region. A corresponding memory controller is also disclosed.

    Abstract translation: 提出了一种访问非易失性存储器的方法。 该方法包括读取非易失性存储器的第一存储器区域并确定第一存储器区域是否包含预定的数据模式。 所述预定数据模式对至少所述第一存储器区域确定的所得到的纠错数据没有影响。 该方法还包括基于第一存储器区域中预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态。 还公开了相应的存储器控​​制器。

    MEMORY READOUT CIRCUIT
    57.
    发明申请
    MEMORY READOUT CIRCUIT 有权

    公开(公告)号：US20250037745A1

    公开(公告)日：2025-01-30

    申请号：US18782285

    申请日：2024-07-24

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Thomas Kern ,  Arndt Voigtlander

    IPC: G11C7/10 ,  G11C7/22

    Abstract: One embodiment describes a memory readout circuit. The memory readout circuit includes a readout node having a capacitance that is discharged by the memory cell to read out a memory cell by means of a cell current, a level detector that is configured to provide a digital output signal and to switch over the output signal when the potential of the readout node (due to the discharge of the readout node) crosses a switching threshold (depending on the selection of the level and the polarity downward or upward, that is to say the switching threshold is overshot or undershot), and a control circuit that is configured to set the switching threshold and/or the switching speed of the level detector depending on the cell current.

    METHOD FOR DETERMINING A CODE WORD
    58.
    发明申请
    METHOD FOR DETERMINING A CODE WORD 有权

    公开(公告)号：US20240411679A1

    公开(公告)日：2024-12-12

    申请号：US18733912

    申请日：2024-06-05

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Michael Goessel

    IPC: G06F12/02

    Abstract: The determination of a code word is proposed, wherein (i) a bit group of n memory cells is read and n states are determined therefrom, the n states being determined in a time domain for each of at least two k-out-of-n codes, the at least two k-out-of-n codes having different k, (ii) the fact of whether a code word is present is determined for each of the at least two codes on the basis of the states, and (iii) when at least one code word is present, the code word of the k-out-of-n code having the largest k is used.

    Access to a memory
    59.
    发明授权
    Access to a memory 有权

    公开(公告)号：US12073880B2

    公开(公告)日：2024-08-27

    申请号：US17844785

    申请日：2022-06-21

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Sebastian Kiesel

    IPC: G11C13/00 ,  G11C7/08 ,  G11C7/10

    CPC classification number: G11C13/004 ,  G11C7/08 ,  G11C7/1039 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054

    Abstract: In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.

    ERROR DETECTION
    60.
    发明公开
    ERROR DETECTION 审中-公开

    公开(公告)号：US20240257893A1

    公开(公告)日：2024-08-01

    申请号：US18424922

    申请日：2024-01-29

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Alexander Klockmann ,  Michael Goessel

    IPC: G11C29/42

    CPC classification number: G11C29/42

    Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.

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