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51.
公开(公告)号:US20220196914A1
公开(公告)日:2022-06-23
申请号:US17131678
申请日:2020-12-22
申请人: Intel Corporation
发明人: Jeremy D. ECTON , Hiroki TANAKA , Brandon C. MARIN , Srinivas V. PIETAMBARAM , Gang DUAN , Bai NIE , Haobo CHEN , Zhichao ZHANG , Sai VADLAMANI , Aleksandar ALEKSOV
IPC分类号: G02B6/12 , H01L23/48 , G02B6/02 , H01L25/065
摘要: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.
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52.
公开(公告)号:US20220187549A1
公开(公告)日:2022-06-16
申请号:US17122352
申请日:2020-12-15
申请人: Intel Corporation
发明人: Hiroki TANAKA , Brandon C. MARIN , Kristof DARMAWKARTA , Robert Alan MAY , Sri Ranga Sai BOYAPATI , Srinivas V. PIETAMBARAM
IPC分类号: G02B6/42
摘要: Embodiments disclosed herein include photonics package with Faraday rotators to improve efficiency. In an embodiment, a photonics package comprises a package substrate and a compute die over the package substrate. In an embodiment, the photonics package further comprises a photonics die over the package substrate. In an embodiment, the compute die is communicatively coupled to the photonics die by a bridge in the package substrate. In an embodiment, the photonics package further comprises an integrated heat spreader (IHS) over the package substrate, and a Faraday rotator passing through the IHS and optically coupled to the photonics die.
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公开(公告)号:US20190393172A1
公开(公告)日:2019-12-26
申请号:US16481392
申请日:2017-03-30
申请人: Intel Corporation
发明人: Srinivas V. PIETAMBARAM , Rahul N. MANEPALLI , Kristof Kuwawi DARMAWIKARTA , Robert Alan MAY , Aleksandar ALEKSOV , Telesphor KAMGAING
摘要: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.
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公开(公告)号:US20180005945A1
公开(公告)日:2018-01-04
申请号:US15197577
申请日:2016-06-29
申请人: Intel Corporation
IPC分类号: H01L23/538 , H01L23/528 , H01L23/522 , H01L23/00 , H01L25/00 , H01L25/065
CPC分类号: H01L23/5381 , H01L23/5226 , H01L23/5283 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0655 , H01L25/50 , H01L2224/13155 , H01L2224/13599 , H01L2224/16227 , H01L2224/16235 , H01L2224/81192 , H01L2924/15192
摘要: Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes a substrate; a silicon interconnect bridge including a plurality of interconnections, the interconnect bridge being embedded in the substrate; and a plurality of contacts on a surface of the substrate, the plurality of contacts being coupled with the plurality of interconnections of the interconnect bridge. The interconnect bridge is bonded in a cavity in the substrate, the cavity being formed by removal of at least one temporary structure from the substrate.
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公开(公告)号:US20240339412A1
公开(公告)日:2024-10-10
申请号:US18130584
申请日:2023-04-04
申请人: Intel Corporation
IPC分类号: H01L23/538 , H01L23/64 , H01L25/065
CPC分类号: H01L23/5386 , H01L23/5384 , H01L23/645 , H01L25/0655 , H01L24/16 , H01L2224/16235 , H01L2924/1511
摘要: Embodiments disclosed herein include an interconnect bridge. In an embodiment, the interconnect bridge comprises a substrate, and a first trace on the substrate. In an embodiment, a first layer is on the first trace, where the first layer comprises a magnetic material. In an embodiment, a second layer is over the substrate, where the second layer comprises an insulating material. In an embodiment, a second trace is embedded in the second layer.
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公开(公告)号:US20240312853A1
公开(公告)日:2024-09-19
申请号:US18121331
申请日:2023-03-14
申请人: Intel Corporation
发明人: Sashi S. KANDANUR , Srinivas V. PIETAMBARAM , Darko GRUJICIC , Brandon C. MARIN , Suddhasattwa NAD , Benjamin DUONG , Gang DUAN , Mohammad Mamunur RAHMAN , Numair AHMED
IPC分类号: H01L23/15 , H01L23/498
CPC分类号: H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838
摘要: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.
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公开(公告)号:US20240217216A1
公开(公告)日:2024-07-04
申请号:US18091028
申请日:2022-12-29
申请人: INTEL CORPORATION
发明人: Kristof DARMAWIKARTA , Tarek A. IBRAHIM , Srinivas V. PIETAMBARAM , Dilan SENEVIRATNE , Jieying KONG , Thomas HEATON , Whitney BRYKS , Vinith BEJUGAM , Junxin WANG , Gang DUAN
CPC分类号: B32B17/10642 , B32B7/12 , B32B17/02 , B65D85/48 , B32B2260/04 , B32B2307/202 , B32B2457/00
摘要: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.
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公开(公告)号:US20240213156A1
公开(公告)日:2024-06-27
申请号:US18089491
申请日:2022-12-27
申请人: Intel Corporation
发明人: Kristof DARMAWIKARTA , Srinivas V. PIETAMBARAM , Gang DUAN , Tarek A. IBRAHIM , Aaron GARELICK , Srikant NEKKANTY , Ravindranath V. MAHAJAN , Rahul N. MANEPALLI
IPC分类号: H01L23/532 , H01L23/00 , H01L23/15 , H01L23/498 , H01L23/522 , H01L23/535 , H01L23/64 , H01L25/065
CPC分类号: H01L23/53209 , H01L23/15 , H01L23/49816 , H01L23/5226 , H01L23/535 , H01L23/642 , H01L24/05 , H01L24/29 , H01L25/0655 , H01L2224/04026 , H01L2224/05567 , H01L2224/29007 , H01L2224/29021 , H01L2224/29101 , H01L2924/1436 , H01L2924/15321
摘要: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core and buildup layers over the core. In an embodiment, a pad is provided on the buildup layers. In an embodiment, a liquid metal well is over the pad.
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公开(公告)号:US20240177918A1
公开(公告)日:2024-05-30
申请号:US18071237
申请日:2022-11-29
申请人: Intel Corporation
发明人: Suddhasattwa NAD , Brandon C. MARIN , Jeremy D. ECTON , Srinivas V. PIETAMBARAM , Gang DUAN , Mohammad Mamunur RAHMAN
CPC分类号: H01F27/2804 , H01F27/306 , H01F41/041 , H01L23/08 , H01L23/3128 , H01F2027/2809 , H01F2027/2819
摘要: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate, a first opening through the core substrate, a second opening through the core substrate and adjacent to the first opening, and a first structure around the core substrate between the first opening and the second opening. In an embodiment, the first structure is electrically conductive. The package core may further comprise a second structure around the core substrate outside of the first opening and the second opening, where the second structure is electrically conductive.
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公开(公告)号:US20240063069A1
公开(公告)日:2024-02-22
申请号:US17892930
申请日:2022-08-22
申请人: Intel Corporation
发明人: Brandon C. MARIN , Rahul N. MANEPALLI , Ravindranath V. MAHAJAN , Srinivas V. PIETAMBARAM , Jeremy D. ECTON , Gang DUAN , Suddhasattwa NAD
IPC分类号: H01L23/13 , H01L23/498 , H01L23/15
CPC分类号: H01L23/13 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/15 , H01L24/16
摘要: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.
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