公开(公告)号：US07144301B2

公开(公告)日：2006-12-05

申请号：US10947458

申请日：2004-09-22

申请人： Kwang-Bok Kim ,  Jae-Kwang Choi ,  Yong-Sun Ko ,  Chang-Ki Hong ,  Kyung-Hyun Kim ,  Jae-Dong Lee

发明人： Kwang-Bok Kim ,  Jae-Kwang Choi ,  Yong-Sun Ko ,  Chang-Ki Hong ,  Kyung-Hyun Kim ,  Jae-Dong Lee

IPC分类号： B24B7/22

CPC分类号： C09G1/02 ,  B24B37/044 ,  B24B49/16 ,  B24B57/02

摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.

摘要翻译： 为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。 第一和第二种浆料是不同的。 例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。 此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

公开(公告)号：US07122478B2

公开(公告)日：2006-10-17

申请号：US10818266

申请日：2004-04-02

申请人： Jeong-Nam Han ,  Woo-Gwan Shim ,  Woo-Sung Han ,  Chang-Ki Hong ,  Sang Jun Choi

发明人： Jeong-Nam Han ,  Woo-Gwan Shim ,  Woo-Sung Han ,  Chang-Ki Hong ,  Sang Jun Choi

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device using a polysilicon layer as an etching mask includes: (a) forming an interlayer dielectric over a semiconductor substrate; (b) forming a polysilicon layer pattern over the interlayer dielectric; (c) forming a contact hole in the interlayer dielectric by etching the interlayer dielectric using the polysilicon layer pattern as an etching mask; (d) removing the polysilicon layer pattern by an etching process that has a large etching selectivity of the polisilicon layer with respect to the interlayer dielectric and about 3% or less etching uniformity; and (e) forming a contact by filling the contact hole with a conductive material.

摘要翻译： 使用多晶硅层作为蚀刻掩模制造半导体器件的方法包括：（a）在半导体衬底上形成层间电介质; （b）在层间电介质上形成多晶硅层图案; （c）通过使用多晶硅层图案作为蚀刻掩模蚀刻层间电介质，在层间电介质中形成接触孔; （d）通过蚀刻工艺去除多晶硅层图案，所述蚀刻工艺对于硅酸盐层相对于层间电介质具有大的蚀刻选择性，蚀刻均匀性为约3％以下; 和（e）通过用导电材料填充接触孔来形成接触。

公开(公告)号：US20060189148A1

公开(公告)日：2006-08-24

申请号：US11358082

申请日：2006-02-22

申请人： Sang-Yong Kim ,  Ji-Hoon Cha ,  Woo-Gwan Shim ,  Chang-Ki Hong ,  Sang-Jun Choi

发明人： Sang-Yong Kim ,  Ji-Hoon Cha ,  Woo-Gwan Shim ,  Chang-Ki Hong ,  Sang-Jun Choi

IPC分类号： H01L21/302 ,  C09K13/00 ,  H01L29/94

CPC分类号： H01L21/32134 ,  C09K13/02 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an etching mask, an etching process may be performed on the metal nitride layer, forming the metal nitride layer pattern. An etchant, which may have an oxidizing agent, a chelate agent and/or a pH adjusting mixture, may perform the etching. The methods may reduce etching damage to a gate insulating layer under the metal nitride layer pattern during the formation of a transistor.

摘要翻译： 提供具有金属氮化物层图案的晶体管，蚀刻剂及其形成方法。 可以在半导体衬底上形成栅极绝缘层和/或金属氮化物层。 掩模层可以形成在金属氮化物层上。 使用掩模层作为蚀刻掩模，可以对金属氮化物层进行蚀刻处理，形成金属氮化物层图案。 可以具有氧化剂，螯合剂和/或pH调节混合物的蚀刻剂可以进行蚀刻。 在形成晶体管期间，这些方法可以减少金属氮化物层图案下的栅极绝缘层的蚀刻损伤。

公开(公告)号：US20060183297A1

公开(公告)日：2006-08-17

申请号：US11130030

申请日：2005-05-16

申请人： Chang-Sup Mun ,  Hyung-Ho Ko ,  Woo-Gwan Shim ,  Chang-Ki Hong ,  Sang-Jun Choi

发明人： Chang-Sup Mun ,  Hyung-Ho Ko ,  Woo-Gwan Shim ,  Chang-Ki Hong ,  Sang-Jun Choi

IPC分类号： H01L21/30 ,  H01L21/302 ,  H01L21/46

CPC分类号： H01L21/31111 ,  H01L21/76224 ,  H01L28/40

摘要： Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an anime salt is added as a counter ion, as represented by R1—OSO3−HA+, R1—CO2−HA+, R1—PO42−(HA+)2, (R1)2—PO4−HA+, or R1—SO3−HA+ where R1 is a straight or branched hydrocarbon group of C4 to C22 and A is ammonia or amine. The etching solution provides a high etching selectivity ratio of an oxide film to a nitride film or a polysilicon film. Therefore, in a semiconductor device fabrication process such as a STI device isolation process or a capacitor formation process, when an oxide film is exposed together with a nitride film or a polysilicon film, the etching solution can be efficiently used in selectively removing only the oxide film.

摘要翻译： 提供了一种用于去除氧化膜的含阴离子表面活性剂的蚀刻溶液，其制备方法以及使用该蚀刻溶液制造半导体器件的方法。 蚀刻溶液包括氢氟酸（HF），去离子水和阴离子表面活性剂。 阴离子表面活性剂是其中加入作为抗衡离子的动物盐的化合物，如R 1〜N 3 O 3 - R 1，R 2，R 1，R 1，...，R 1， （R 1）2 - - - - - （4）其中R 1，R 2， / SUB>）2 + 或 其中R 1是C 4的直链或支链烃基，其中R 1是直链或支链C 1 -C 4烷基， C 22和A是氨或胺。 蚀刻溶液提供氧化膜与氮化物膜或多晶硅膜的高蚀刻选择性比。 因此，在诸如STI器件隔离处理或电容器形成工艺的半导体器件制造工艺中，当氧化物膜与氮化物膜或多晶硅膜一起暴露时，可以有效地使用蚀刻溶液来仅选择性地除去氧化物 电影。

公开(公告)号：US20050272218A1

公开(公告)日：2005-12-08

申请号：US11145308

申请日：2005-06-03

申请人： Young-Rae Park ,  Young-Ho Koh ,  Chang-Ki Hong

发明人： Young-Rae Park ,  Young-Ho Koh ,  Chang-Ki Hong

IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

摘要： A method of forming a cylindrical lower electrode of a capacitor in which metal is used as a lower electrode of a capacitor. A metal capping layer is used in order to protect the inner walls of the cylindrical metal lower electrode. A sacrificial insulating layer is patterned to form an aperture for forming the lower electrode. A metal lower electrode layer and the metal capping layer are sequentially formed. In order to electrically separate adjacent metal lower electrodes from each other, the metal capping layer and the metal lower electrode layer are simultaneously planarized until the sacrificial insulating layer is exposed. The sacrificial insulating layer and the metal capping layer that resides in the aperture are removed such that the cylindrical metal lower electrode having inner and outer walls is completed. Therefore, it is possible to simultaneously palanarize the metal capping layer and the metal lower electrode layer with respect to the sacrificial insulating layer such that it is possible to simplify processes for forming the lower electrodes.

摘要翻译： 一种形成电容器的圆柱形下电极的方法，其中金属用作电容器的下电极。 为了保护圆柱形金属下电极的内壁，使用金属覆盖层。 图案化牺牲绝缘层以形成用于形成下电极的孔。 依次形成金属下电极层和金属覆盖层。 为了将相邻的金属下电极彼此电分离，金属覆盖层和金属下电极层同时被平坦化，直到牺牲绝缘层暴露。 除去驻留在孔中的牺牲绝缘层和金属覆盖层，使得具有内壁和外壁的圆柱形金属下电极完成。 因此，可以相对于牺牲绝缘层同时进行金属覆盖层和金属下电极层的平坦化，使得可以简化用于形成下电极的工艺。

公开(公告)号：US20050250316A1

公开(公告)日：2005-11-10

申请号：US11168894

申请日：2005-06-29

申请人： Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son

发明人： Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son

IPC分类号： H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L27/24

CPC分类号： H01L21/7684 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： Methods are provided for fabricating contacts in integrated circuit devices, such as phase-change memories. A protection layer and a sacrificial layer are sequentially formed on a semiconductor substrate. A contact hole is formed through the sacrificial layer and the protection layer. A conductive layer is formed on the sacrificial layer and in the contact hole, and portions of the conductive layer and the sacrificial layer are removed to expose the protection layer and form a conductive plug protruding from the protection layer. A protruding portion of the conductive plug removed to leave a contact plug in the protection layer. A phase-change data storage element may be formed on the contact plug.

摘要翻译： 提供了用于在诸如相变存储器的集成电路器件中制造触点的方法。 在半导体衬底上依次形成保护层和牺牲层。 通过牺牲层和保护层形成接触孔。 在牺牲层和接触孔中形成导电层，并且去除导电层和牺牲层的部分以露出保护层并形成从保护层突出的导电插塞。 去除导电塞的突出部分，以在保护层中留下接触塞。 可以在接触插塞上形成相变数据存储元件。

公开(公告)号：US20050239672A1

公开(公告)日：2005-10-27

申请号：US11104829

申请日：2005-04-13

申请人： Chang-Sup Mun ,  Doo-Won Kwon ,  Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi

发明人： Chang-Sup Mun ,  Doo-Won Kwon ,  Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi

IPC分类号： H01L21/304 ,  B08B3/00 ,  C11D1/00 ,  C11D1/66 ,  C11D1/72 ,  C11D3/02 ,  C11D11/00 ,  C30B1/00 ,  H01L21/306 ,  H01L21/308

CPC分类号： H01L21/02052 ,  C11D1/66 ,  C11D1/72 ,  C11D3/044 ,  C11D11/0047 ,  H01L21/3081 ,  Y10S134/902

摘要： Disclosed are a cleaning solution for preventing damage of a silicon germanium layer when cleaning a semiconductor device including the silicon germanium layer and a cleaning method using the same. The cleaning solution of a silicon germanium layer includes from about 0.01 to about 2.5 percent by weight of a non-ionic surfactant with respect to 100 percent by weight of the cleaning solution, about 0.05 to about 5.0 percent by weight of an alkaline compound with respect to the cleaning solution and a remaining amount of pure water. The damage to an exposed silicon germanium layer can be prevented when cleaning a silicon substrate having a silicon germanium layer. Impurities present on the surface portion of the silicon germanium layer can be effectively removed.

摘要翻译： 公开了一种用于在清洁包括硅锗层的半导体器件时的防止硅锗层损坏的清洁溶液以及使用其的清洁方法。 硅锗层的清洁溶液包括约0.01至约2.5重量％的非离子表面活性剂相对于100重量％的清洁溶液，约0.05至约5.0重量％的碱性化合物，相对于 到清洁溶液和剩余量的纯水。 当清洁具有硅锗层的硅衬底时，可以防止暴露的硅锗层的损坏。 可以有效地除去存在于硅锗层的表面部分上的杂质。

公开(公告)号：US20050170981A1

公开(公告)日：2005-08-04

申请号：US11038585

申请日：2005-01-19

申请人： Chang-Sup Mun ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Woo-Sung Han

发明人： Chang-Sup Mun ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Woo-Sung Han

IPC分类号： C11D1/12 ,  C11D1/14 ,  C11D3/00 ,  C11D3/20 ,  C11D3/34 ,  C11D11/00 ,  C11D1/00

CPC分类号： H01L21/02071 ,  C11D1/146 ,  C11D3/0073 ,  C11D3/2031 ,  C11D3/2055 ,  C11D3/3409 ,  C11D3/3427 ,  C11D11/0047

摘要： A cleaning composition comprises an alkali solution, pure water, and a surfactant represented by the following chemical formula: R1-OSO3—HA+ wherein R1 is one selected from a group consisting of a butyl group, an isobutyl group, an isooctyl group, a nonyl phenyl group, an octyl phenyl group, a decyl group, a tridecyl group, a lauryl group, a myristyl group, a cetyl group, a stearyl group, an oleyl group, a licenoleyl group and a behnyl group, and A is one selected from a group consisting of ammonia, ethanol amine, diethanol amine and triethanol amine.

摘要翻译： 清洁组合物包含碱溶液，纯水和由以下化学式表示的表面活性剂：其中R 1是选自下列化学式的一种： 由丁基，异丁基，异辛基，壬基苯基，辛基苯基，癸基，十三烷基，月桂基，肉豆蔻基，十六烷基，硬脂基，油基 基团，丙烯酰基和苯丙基，A是选自氨，乙醇胺，二乙醇胺和三乙醇胺中的一种。

公开(公告)号：US20050074948A1

公开(公告)日：2005-04-07

申请号：US10949426

申请日：2004-09-24

申请人： Hyung-Ho Ko ,  Woo-Gwan Shim ,  Yu-Kyung Kim ,  Chang-Ki Hong ,  Sang-Jun Choi

发明人： Hyung-Ho Ko ,  Woo-Gwan Shim ,  Yu-Kyung Kim ,  Chang-Ki Hong ,  Sang-Jun Choi

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： In a method of manufacturing a shallow trench isolation (STI) structure using a HF vapor etching process according to some embodiments of the invention, a trench is formed in a semiconductor substrate. A buffer layer and a first insulating layer, which fill the trench, are formed. A portion of the first insulating layer is removed by performing an etching process using HF vapor, thereby removing a void existing in the first insulating layer. A second insulating layer filling the trench is formed on the etched first insulating layer. Other embodiments of the invention are described and claimed.

摘要翻译： 在根据本发明的一些实施例的使用HF蒸汽蚀刻工艺制造浅沟槽隔离（STI）结构的方法中，在半导体衬底中形成沟槽。 形成填充沟槽的缓冲层和第一绝缘层。 通过使用HF蒸气进行蚀刻处理来去除第一绝缘层的一部分，从而去除存在于第一绝缘层中的空隙。 在蚀刻的第一绝缘层上形成填充沟槽的第二绝缘层。 描述和要求保护本发明的其它实施例。

公开(公告)号：US06642105B2

公开(公告)日：2003-11-04

申请号：US10131010

申请日：2002-04-24

申请人： Kyung-Hyun Kim ,  Chang-Ki Hong ,  U-In Chung ,  Bum-Soo Kim ,  Yoo-Cheol Shin ,  Kyu-Chan Park

发明人： Kyung-Hyun Kim ,  Chang-Ki Hong ,  U-In Chung ,  Bum-Soo Kim ,  Yoo-Cheol Shin ,  Kyu-Chan Park

IPC分类号： H01L21336

CPC分类号： H01L21/823462 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541

摘要： A semiconductor device having multi-gate insulating layers and methods of fabricating the same are provided. The semiconductor device includes an isolation region disposed at a predetermined region of a semiconductor substrate. The isolation region defines at least one first active region and at least one second active region. The first active region is covered with a first gate insulating layer, and the second active region is covered with a second gate insulating layer which is thinner than the first gate insulating layer. Preferably, the top surface of the first gate insulating layer has the same height as the that of the second gate insulating layer. The isolation region is filled with an isolation layer which preferably covers the entire sidewalls of the first and second gate insulating layers. A typical method includes the step of selectively forming a first gate insulating layer at a predetermined region of a semiconductor substrate. A second gate insulating layer which is thinner than the first insulating layer is selectively formed at the surface of the semiconductor substrate adjacent to the first gate insulating layer. Preferably, the bottom surface of the first gate insulating layer is lower than that of the second gate insulating layer. The first and second gate insulating layers are covered with a conductive layer. The conductive layer, the first and second gate insulating layers, and the substrate are etched to form an isolation region, for example, a trench region, defining a first active region under the first gate insulating layer and a second active region under the second gate insulating. An isolation layer is formed in the trench region. The isolation layer preferably covers the entire sidewalls of the first and second gate insulating layers.